nau85l40音频采集verilog code（I2S）

module NAU85L40_recvdata_module(//INPUT
                                sys_nrst,
                                audio_bclk, //16KHZ*32bits*2 = 1024KHZ
                                audio_lclk,
sdi_12,   //NAU85L40 PIN DO12
sdi_34,   //NAU85L40 PIN DO34
//OUTPUT
sdo_12_L,
sdo_12_R,
sdo_34_L,
sdo_34_R,
);


parameter audio_samplerate=16000; //hz
parameter audio_datawidth=24; //bit
parameter audio_channel=2; //L & R
parameter nau85l40_datawidth=32; //bit


input sys_nrst, audio_bclk, audio_lclk;
input sdi_12, sdi_34;
output reg[audio_datawidth-1:0]sdo_12_L, sdo_12_R;
output reg[audio_datawidth-1:0]sdo_34_L, sdo_34_R;


reg lclkdel;
reg [nau85l40_datawidth:0] sdreg_12,sdreg_34;
reg [7:0] cnt = 0;
wire lclkp;


always @ (posedge audio_bclk or negedge sys_nrst)
begin
    if (~sys_nrst)
    begin
        lclkdel <= 1'b0;
    end
    else
    begin
        lclkdel <= audio_lclk;
end
end


assign lclkp = lclkdel ^ audio_lclk;


always @(posedge audio_bclk or negedge sys_nrst)
begin
    if (~sys_nrst)
    begin
        sdreg_12 <= 0;
        sdreg_34 <= 0;
    end
    else
    begin
        sdreg_12[nau85l40_datawidth:0] <= {sdreg_12[nau85l40_datawidth-1:0],sdi_12};
        sdreg_34[nau85l40_datawidth:0] <= {sdreg_34[nau85l40_datawidth-1:0],sdi_34};
    end
end


always @(posedge audio_bclk or negedge sys_nrst)
begin
    if (~sys_nrst) cnt <= 0;
else if(lclkp == 1) cnt <= 0;
else cnt <= cnt+1;
end


always @(negedge audio_bclk or negedge sys_nrst)
begin
    if (~sys_nrst)
    begin
        sdo_12_L <= 0;
        sdo_12_R <= 0;
        sdo_34_L <= 0;
        sdo_34_R <= 0;
    end
    else
    begin
        if (cnt == 0 && audio_lclk == 1)    //Left channel data is vaild
        begin
    sdo_12_L <= sdreg_12[nau85l40_datawidth-1:8];
sdo_34_L <= sdreg_34[nau85l40_datawidth-1:8];
        end
        else if (cnt == 0 && audio_lclk == 0) //Right channel data is valid
begin
    sdo_12_R <= sdreg_12[nau85l40_datawidth-1:8];
sdo_34_R <= sdreg_34[nau85l40_datawidth-1:8];
end
else
begin
/*
    sdo_12_L <= sdo_12_L;
sdo_12_R <= sdo_12_R;
sdo_34_L <= sdo_34_L;
sdo_34_R <= sdo_34_R;
*/
end
    end
end


endmodule