uart

arch/arm/boot/dts/imx6qdl-sabresd.dtsi

&uart1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart1>;
 status = "okay";
};

&uart2 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart2>;
 status = "okay";
};

&uart4 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart4>;
 status = "okay";
};

&uart5 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart5_1>;
 status = "okay";
};

 
&iomuxc {

 pinctrl_uart1: uart1grp {
   fsl,pins = <
    MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
    MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
   >;
  };
  
  pinctrl_uart2: uart2grp {
   fsl,pins = <
    MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
    MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
    MX6QDL_PAD_SD3_CMD__UART2_CTS_B     0x1b0b1
    MX6QDL_PAD_SD3_CLK__UART2_RTS_B     0x1b0b1
   >;
  };
  
  pinctrl_uart4: uart4grp {
   fsl,pins = <
    MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
    MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
   >;
  };
  
  pinctrl_uart5_1: uart5grp-1 {
   fsl,pins = <
    MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
    MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
    /*
    MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
    MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
    */
   >;
  };