After reading the article pervious, you may wonder how the system boot up.
This time I will summary of that topic.
As you know, when power on or reset happened, the system will run the bios.
This comes a question: how the cpu accsses the memory which it wants?
I will talk some middle ages x86 system this time. Now, let's start.
When hard boot, the cpu will run code at the reset vector "0xFFFFFFF0h" after being
masked by A20 that is 0xFFFF0h and this is where the bios sits, but how dose the cpu access it?
This because the accessing to an address is directed by the mch(disappered in nowadays system).
There are a group of registers in mch which is using for this such as TOM and PAM. When get request from cpu,it will examine whethre the address is belong to its, like whether it is below the value in TOM, and then whether the PAMF0 is marked disabled. When PAMF0 is marked
disabled, the MCH will direct the request to ICH, and ICH will response to this address, which
can be decoded by it as the bios. So the cpu run the bios.
"To end like this?"
-----Jon Irenicus.
The answer is "No, absolutely not!". Our story has not ended yet.
Through the MCH can received the request from CPU, it can request to the CPU too.
This is used by what is called the MSI tech. When PCI device wants to interrupt CPU, instead of
sending signal to CPU, it can develiver a interrupt message to CPU by the MCH.
When MCH initiates the interrupt message transcation:
The MCH acts as the transaction's Request Agent.
The transaction is a memory transaction but the snoop in the processor caches will result in a miss (because the Local APIC's register space is designated as UC in the MTRRs).
The only valid snoop results would be a miss (neither HIT# nor HITM# asserted), or a snoop stall (both HIT# and HITM# asserted). When the processors are the actual targets of the transaction, none of them act as the transaction's Response Agent. Rather, in the transaction's Response Phase, the MCH supplies the appropriate response for a memory write transaction (i.e., the No Data Response).
In the Response Phase, the MCH asserts the TRDY# signal to indicate that the processors are ready to accept the write data. Acting as the Request Agent, upon detecting the assertion of the TRDY# signal, the MCH asserts the DBSY# signal to takes ownership of the data bus. It then drives the 32-bits of write data and asserts DRDY# to indicate its presence on the data bus.
The CPU can also send interrupt message by its memory-mapped register ICR.The procedure is:
The processor acts as the transaction's Request Agent.
The transaction is a memory transaction but the snoop in the processor caches will result in a miss (because the Local APIC's register space is designated as UC in the MTRRs). The only valid snoop results would be a miss (neither HIT# nor HITM# asserted), or a snoop stall (both HIT# and HITM# asserted).
The device targeted by the message transaction could be either the other processors (if it's an IPI message), or the IO APIC (if it's a write to the IO APIC's EOI register). In either case, the MCH acts as the Response Agent in the transaction's Response Phase. In the transaction's Response Phase, the MCH supplies the appropriate response for a memory write transaction (i.e., the No Data Response).
In the Response Phase, the MCH asserts the TRDY# signal to indicate one of the following:
If it's an IPI message, that the processors are ready to accept the write data.
If the message targets the IO APIC (e.g., it's a write to the IO APIC's EOI register), that the MCH is ready to accept the write data.Upon detecting the assertion of the TRDY# signal, the processor that initiated the transaction asserts the DBSY# signal to takes ownership of the data bus. It then drives the 32-bits of write data and asserts DRDY# to indicate its presence on the data bus.
OK, this time we just talk so much.
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