project : dessect Nand read from Vivi
instruction : dessect Nand read from ViVi step by step.
(1) the below fragment from ViVi is represent for reading Nand flash to memory.
int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
{
int i, j;
if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
return -1; /* invalid alignment */
}
NAND_CHIP_ENABLE; // see comment [ comment A ]
for(i=start_addr; i < (start_addr + size);) {
/* READ0 */
NAND_CLEAR_RB; // see comment [ comment B ]
NFCMD = 0; see comment [ comment C ]
/* Write Address */
NFADDR = i & 0xff; //see comment [ comment D ]
NFADDR = (i >> 9) & 0xff; //see comment [ comment D ]
NFADDR = (i >> 17) & 0xff; //see comment [ comment D ]
NFADDR = (i >> 25) & 0xff; //see comment [ comment D ]
NAND_DETECT_RB; //see comment [ comment E ]
for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
*buf = (NFDATA & 0xff); //see comment [ comment F ]
buf++;
}
}
NAND_CHIP_DISABLE; // [ comment A ]
return 0;
}
======================================================================================
[ comment A ]
#define NAND_CHIP_ENABLE (NFCONT &= ~(1<<1))
#define NAND_CHIP_DISABLE (NFCONT |= (1<<1))
CONTROL REGISTER
------------------------------------------------------------------------------------
Register Address R/W Description Reset Value
------------------------------------------------------------------------------------
NFCONT 0x4E000004 R/W NAND flash control register 0x0384
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
NFCONT Bit Description Initial State
------------------------------------------------------------------------------------
Reg_nCE [1] NAND Flash Memory nFCE signal control 1
0: Force nFCE to low (Enable chip select)
1: Force nFCE to high (Disable chip select)
Note: During boot time, it is controlled
automatically.
This value is only valid while MODE bit is 1
------------------------------------------------------------------------------------
======================================================================================
[ comment B ]
#define NAND_CLEAR_RB (NFSTAT |= (1<<2))
------------------------------------------------------------------------------------
NFSTAT Bit Description Initial State
------------------------------------------------------------------------------------
RnB_TransDetect [2] When RnB low to high transition is 0
occurred, this value set and issue
interrupt if enabled. To clear this
value write ‘1’.
0: RnB transition is not detected
1: RnB transition is detected
Transition configuration is set in
RnB_TransMode (NFCONT[8]).
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
Pin Name Pin Function
------------------------------------------------------------------------------------
RnB READY/BUSY OUTPUT
The R/B output indicates the status of the device operation.
When low, it indicates that a program, erase or random read
operation is in process and returns to high state upon
completion. It is an open drain output and does not float to
high-z condition when the chip is deselected or when outputs
are disabled.
------------------------------------------------------------------------------------
======================================================================================
[ comment C ]
#define NFCMD bNAND_CTL(0x08)
COMMAND REGISTER
------------------------------------------------------------------------------------
Register Address R/W Description Reset Value
------------------------------------------------------------------------------------
NFCMMD 0x4E000008 R/W NAND flash command set register 0x00
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
NFCMMD Bit Description Initial State
------------------------------------------------------------------------------------
Reserved [15:8] Reserved 0x00
NFCMMD [7:0] NAND flash memory command value 0x00
------------------------------------------------------------------------------------
======================================================================================
[ comment D ]
#define NFADDR bNAND_CTL(0x0c)
ADDRESS REGISTER
------------------------------------------------------------------------------------
Register Address R/W Description Reset Value
------------------------------------------------------------------------------------
NFADDR 0x4E00000C R/W NAND flash address set register 0x0000XX00
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
REG_ADDR Bit Description Initial State
------------------------------------------------------------------------------------
Reserved [15:8] Reserved 0x00
------------------------------------------------------------------------------------
NFADDR [7:0] NAND flash memory address value 0x00
------------------------------------------------------------------------------------
======================================================================================
[ comment E ]
#define NAND_DETECT_RB { while(! (NFSTAT&(1<<2)) );}
#define NFSTAT bNAND_CTL(0x20)
NFCON STATUS REGISTER
------------------------------------------------------------------------------------
Register Address R/W Description Reset Value
------------------------------------------------------------------------------------
NFSTAT 0x4E000020 R/W NAND flash operation status register 0xXX00
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
NFSTAT Bit Description Initial State
------------------------------------------------------------------------------------
RnB_TransDetect [2] When RnB low to high transition is 0
occurred, this value set and issue
interrupt if enabled. To clear this
value write ‘1’.
0: RnB transition is not detected
1: RnB transition is detected
Transition configuration is set in
RnB_TransMode (NFCONT[8]).
------------------------------------------------------------------------------------
======================================================================================
[ comment F ]
#define NFDATA __REGb(0x4e000000 + (0x10))
DATA REGISTER
------------------------------------------------------------------------------------
Register Address R/W Description Reset Value
------------------------------------------------------------------------------------
NFDATA 0x4E000010 R/W NAND flash data register 0xXXXX
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
NFDATA Bit Description Initial State
------------------------------------------------------------------------------------
NFDATA [31:0] NAND flash read/program data value for I/O 0xXXXX
Note: Refer to data register configuration
in Page 6-5.
------------------------------------------------------------------------------------
======================================================================================
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