Nand flash usage

project    : Nand Flash ( Samsung K9F1208 ) operator
instruction: Nand Flash reading , writting, erase, mark out the invaild block and so on.

refer to Samsung K9F1208 datasheet.

(1) Nandflash summary.
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Nandflash.jpg (refer to K9F1208 datasheet)

The K9F1208X0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte(x8 device), 264word(x16 device) data register is connected to memory
cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The
memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different
page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a
block. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase
operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the
bit by bit erase operation is prohibited on the K9F1208X0A.

The K9F1208X0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires 26
addresses(X8 device) or 25 addresses(X16 device), thereby requiring four cycles for byte-level addressing: column address, low row
address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required
command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by
writing specific commands into the command register. Table 1 defines the specific commands of the K9F1208X0A.


（译:）
K9F1208X0A存储器容量528M比特，由131,072行（页）x 528列矩阵组成。最尾的16列被安排为从512到527. 这些528字节（x8存储器），264字（x16存储器）
数据存储组被连接在一起是为了用来帮助在I/O缓冲跟存储器之间页读写操作的数据传输。这些存储组由16个单元串行连接在一起形成一个Nand结构。每个16单元
存放在不同的页。 一个块有2组Nand结构串在一起组成。 一个Nand结构由16个单元组成。 一个块总共有135168个Nand单元（135168bit=528(bytes)X32(pages)*8(bit)).
这些存储单元组织图如图2. 存储器读写操作基于一个页来执行的，而擦除操作基于块来执行的。存储设备总共由4096个独立可擦除的16K-byte块组成，它指示了
在K9F1208X0A上一位一位的擦除操作是不允许的。

K9F1208X0A 使用8位I/O的地址复用技术。 这样就可以显著地减少引脚数和方便系统今后升级而不改变系统板原来的设计。命令，地址和数据都通过I/O口来写，
依赖使能WE为低电平当CE是地电平。数据在WE的上升缘被锁存。 命令锁存（使能CLE）和地址锁存（使能ALE）都独立地通过I/O引脚用来命令和地址复用。64M
字节物理空间需要26位地址（X8 存储器）或者25位地址（X16存储器），因此需要用4个周期：列地址， 行（低8）地址和行（高8）地址这样的顺序来字寻址。
页读和页写在请求命令输入之后也同样需要四个地址周期来寻址。块擦除操作则需要用3个地址周期来寻址。设备操作被选择只是通过写指定的命令到命令寄存器。
表1定义K9F1208X0A一些指定命令.

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(2) checking the invalid block.  (refer to K9F1208 datasheet)
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Nand_invalid_block.jpg

NAND Flash Technical Notes
Identifying Invalid Block(s)
Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaran-
teed to be a valid block, does not require  Error Correction up to 1K program/erase cycles.

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the
1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8
device) or 256 and 261(X16 device).  Since the invalid block information is also erasable in most cases, it is impossible to recover the
information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original
invalid block information and create the invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of
the original invalid block information is prohibited.

（译：）
失效块被定义为这块包含一个或多个失效位，这些失效位是否可靠，三星公司不做任何的保证。关于这些失效块的信息也被叫做坏块信息。带有坏块的存储设备
跟那些没任何坏块的设备具备同样的属性，也有同样的AC跟DC特征。一个坏块不会影响好块的执行，因为它通过选择的晶体管从位线和共同的源线独立开来的。
系统设计必须能够通过地址映射来憋开坏块。不过在00h地址的第一个块被保证是有效的，不需要任何的错误纠正直到上限1K的范围。

所有的存储设备本地单元被擦除为FFh，除非失效块的信息被写比装载时还早，坏块的状态通过在剩余区域的第6个字节（x8存储器）或第1字（X16存储器）被定义。
三星公司保证在第1个和第2个页里的任何失效块里的第517列（x8存储器）或者 第261列（X16存储器）不会存在非FFH（x8存储器）或者 非FFFFh（x16存储器）的
值。因为坏块信息在大部分情况下也同样可以可擦除，它不可能恢复这些信息一旦被擦除后。因此，系统必须能够基于原来的坏块信息识别坏块和根据图4的建议
创建坏块表。任何故意的擦除原始坏块信息都是不允许的。

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(3) Nandflash program. (refer to K9F1208 datasheet)
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Nand_program.jpg


NAND Flash Technical Notes (Continued)
Error in write or read operation

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done.  Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block.  To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.

（译：）
在存储器的生命期里，在使用Nand flash开发时会出现新增的坏块可能。请参考真实数据的质量报告。当实现一个高度可靠的系统时，下面可能的失败模式应该
被考虑进来。在擦除或写入后读失败的时候，应该使用块代替来完成。 因为在同一个块里，在页编程时写入失败不会影响到其他页的数据，块代替可以使用一个
页大少的缓冲来执行，通过查找一个空的块跟重写当前的目标数据和复制被代替块的其余部分。为了改进高效的存储空间，推荐由于单个位错误引起的读或者验证
失败通过用ECC纠正，而不是用块代替。所说的新增块失效率不会包含这些被恢复的块的。

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(4) Nandflash Reading. (refer to K9F1208 datasheet)
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Nand_Read.jpg

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(5) NandFlash erasing. (refer to K9F1208 datasheet)
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Nand_Erase.jpg

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(6) Nandflash pointer accessor. (refer to K9F1208 datasheet)
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Nand_Point.jpg

Samsung NAND Flash  has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands,  the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Pointer Operation of K9F1208X0A(X8)

（译：）
三星Nand flash有三个地址指针命令来代替2个最重要的列地址。'00h'命令设置指针访问'A'区域（0～255byte）， '01h'命令设置指针访问'B'区域（256～511byte)
和'50h'命令设置指针访问'C'区域（512～527byte). 使用这些命令，开始列地址可以被设置为整个页（0～527byte）的任何地方。'00h'或者'50h'是保持着直到另
一个地址指针命令输入。 '01h'命令，只能有效的支持一个操作。一旦使用'01h'命令在任何读写，擦除，power_up操作之后，地址指针自己返回到'A'区域。在写
数据到'A'或者'C'区域时，'00h'或者'50h'命令必须在写'80h'命令之前被输入进去。一个完全的读操作优先于'80h'命令不是必须。如果开始写数据到'B'区域，那么
'01h'命令在'80h'命令写入前必须被输入正确。

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