Interrupts and Exceptions（五）

The Advanced Programmable Interrupt Controller (APIC)

The previous description refers to PICs designed for uniprocessor systems. If the system includes a single CPU, the output line of the master PIC can be connected in a straightforward way to the INTR pin the CPU. However, if the system includes two or more CPUs, this approach is no longer valid and more sophisticated PICs are needed.

如果系统只有一个CPU，主PIC的输出线可以直接连接到CPU的INTR管脚。然而，如果系统包含2个或更大CPU，这种方法不再有用，需要更复杂的PIC。

Being able to deliver interrupts to each CPU in the system is crucial for fully exploiting the parallelism of the SMP architecture. For that reason, Intel introduced starting with Pentium III a new component designated as the I/O Advanced Programmable Interrupt Controller (I/O APIC). This chip is the advanced version of the old 8259A Programmable Interrupt Controller; to support old operating systems, recent motherboards include both types of chip. Moreover, all current 80 x 86 microprocessors include a local APIC. Each local APIC has 32-bit registers, an internal clock; a local timer device; and two additional IRQ lines, LINT 0 and LINT 1, reserved for local APIC interrupts. All local APICs are connected to an external I/O APIC, giving rise to a multi-APIC system.

对于完全采用并行机制的SMP架构来说，那个将中断送到系统中每个CPU很关键。为此，Intel在Pentium III中引入了一种新的组件，叫做I/O APIC（I/O 高级可编程中断控制器）。这个芯片是老的8259A可编程中断控制器的高级版本；为了支持旧的操作系统，当前的主板包括了这两种类型的芯片。此外，如今所有的x86微处理器都自带了一个局部APIC。每个局部APIC有32bit寄存器，一个周期时钟，一个局部计时设备和两个额外的IRQ线，LINT 0和LINT 1，为本地APIC中断保留。所有的局部APIC都连到一个外部的I/O APIC，形成了一个多APIC系统。

Figure 4-1 illustrates in a schematic way the structure of a multi-APIC system. An APIC bus connects the "frontend" I/O APIC to the local APICs. The IRQ lines coming from the devices are connected to the I/O APIC, which therefore acts as a router with respect to the local APICs. In the motherboards of the Pentium III and earlier processors, the APIC bus was a serial three-line bus; starting with the Pentium 4, the APIC bus is implemented by means of the system bus. However, because the APIC bus and its messages are invisible to software, we won't give further details.

一条APIC总线将I/O APIC前端连到局部APIC。来自设备的IRQ线连到I/O APIC，因此它相当于局部APIC的路由器。在Pentium III和较早的处理器的主板上，APIC总线是串行的3线总线；从Pentium 4 开始，APIC总线通过系统总线来实现。

The I/O APIC consists of a set of 24 IRQ lines, a 24-entry Interrupt Redirection Table, programmable registers, and a message unit for sending and receiving APIC messages over the APIC bus. Unlike IRQ pins of the 8259A, interrupt priority is not related to pin number: each entry in the Redirection Table can be individually programmed to indicate the interrupt vector and priority, the destination processor, and how the processor is selected. The information in the Redirection Table is used to translate each external IRQ signal into a message to one or more local APIC units via the APIC bus.

I/O APIC由24条IRQ线、一个24条目的中断重定向表、可编程寄存器和一个通过APIC总线发送和接收APIC消息的消息单元组成。与8259A的中断线不同，中断优先级与管脚号无关；重定向表中的每个条目可被编程分为显示中断向量和优先级，目标处理器，处理器是如何选择的。重定向表中的信息用来将每个尾部IRQ信号转换为通过APIC总线发送给一个或更多的局部APIC单元的消息。

Interrupt requests coming from external hardware devices can be distributed among the available CPUs in two ways:

来自外部硬件设备的中断请求可以用下列两种方式在可用的CPU之间分配：

Static distribution

The IRQ signal is delivered to the local APICs listed in the corresponding Redirection Table entry. The interrupt is delivered to one specific CPU, to a subset of CPUs, or to all CPUs at once (broadcast mode).

IRQ信号发送给对应重定向表条目中所列的局部APIC。中断被送到某一个特定的CPU，或几个CPU，或一次给所有的CPU（广播模式）。

Dynamic distribution

The IRQ signal is delivered to the local APIC of the processor that is executing the process with the lowest priority.

IRQ信号送给正在执行最低优先级进程的处理器的局部APIC。

Every local APIC has a programmable task priority register (TPR), which is used to compute the priority of the currently running process. Intel expects this register to be modified in an operating system kernel by each process switch.

每个局部APIC有一个TPR寄存器（可编程任务优先级寄存器），它用来计算当前运行进程的优先级。Intel系统期望这个寄存器在每次进程切换中由操作系统内核修改。

If two or more CPUs share the lowest priority, the load is distributed between them using a technique called arbitration. Each CPU is assigned a different arbitration priority ranging from 0 (lowest) to 15 (highest) in the arbitration priority register of the local APIC.

如果2个或更多的CPU共享最低的优先级，则使用一种将在仲裁的计数在它们之间进行负载划分。每个CPU分配了一个不同的仲裁优先级，从最低0到最高15，存放在局部APIC的仲裁优先级寄存器中。

Every time an interrupt is delivered to a CPU, its corresponding arbitration priority is automatically set to 0, while the arbitration priority of any other CPU is increased. When the arbitration priority register becomes greater than 15, it is set to the previous arbitration priority of the winning CPU increased by 1. Therefore, interrupts are distributed in a round-robin fashion among CPUs with the same task priority.^[*]

每次中断送到CPU，它对应的仲裁优先级自动设为0，而其他任何CPU的仲裁优先级则增加。当仲裁优先级寄存器变得比15大时，它设置为获胜CPU的前一个仲裁优先级值加1.因此，中断以环的方式在具有相同任务优先级的ＣＰＵ中分配。

^[*] The Pentium 4 local APIC doesn't have an arbitration priority register; the arbitration mechanism is hidden in the bus arbitration circuitry. The Intel manuals state that if the operating system kernel does not regularly update the task priority registers, performance may be suboptimal because interrupts might always be serviced by the same CPU. 

Pentium4的局部APIC没有这样的仲裁优先级寄存器；仲裁机制隐藏在总线仲裁电路中。Intel手册声名如果操作系统没有定时地更新任务优先级寄存器，性能可能会降低，因为中断总是由同一个ＣＰＵ响应。   

Besides distributing interrupts among processors, the multi-APIC system allows CPUs to generate interprocessor interrupts. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.

除了在处理器间分配中断，多ＡＰＩＣ系统允许ＣＰＵ生成处理器内部中断。当某个ＣＰＵ希望发送一个中断给另一个中断时，它保存中断向量并在它自己的局部ＡＰＩＣ的ＩＣＲ（中断命令寄存器）中标识目标的局部ＡＰＩＣ。然后一个消息通过ＡＰＩＣ总线送到目标的ＡＰＩＣ，再由它发出一个对应的中断给它自己的CPU。

Interprocessor interrupts (in short, IPIs) are a crucial component of the SMP architecture. They are actively used by Linux to exchange messages among CPUs (see later in this chapter).

处理器内部中断（简称IPI）是SMP架构的关键成分。它们在Linux活跃地使用，在CPU间交换消息。

Many of the current uniprocessor systems include an I/O APIC chip, which may be configured in two distinct ways:

·         As a standard 8259A-style external PIC connected to the CPU. The local APIC is disabled and the two LINT 0 and LINT 1 local IRQ lines are configured, respectively, as the INTR and NMI pins.

作为一标准的6259A风格的外部PIC连接到CPU。局部APIC关闭，LINT 0和LINT 1这两条IRQ线分别配置为INTR和NMI管脚。

·         As a standard external I/O APIC. The local APIC is enabled, and all external interrupts are received through the I/O APIC.

作为标准的外部I/O APIC.局部APIC开启，所有的外部中断都是通过I/O APIC接收。