Figure 4-2. Indirect Registers and Firmware memory map
Table 4-1. Direct Register Memory Map
ADDRESS NAME DESCRIPTION R/W LENGTH
0x00 PIXEL Pixel FIFO Access Register R/W [31..0]
0x01 CODE Compressed Code Stream Access Register R/W [31..0]
0x02 ATTR Attribute FIFO Access Register R/W [31..0]
0x03 Reserved Reserved R/W [31..0]
0x04 Reserved Reserved R/W [31..0]
0x05 EIRQIE External Interrupt Enabled R/W [15..0]
0x06 EIRQFLG External interrupt Flags R/W [15..0]
0x07 SWFLAG Software Flag Register R [15..0]
0x08 BMODE Bus Mode Configuration Register R/W [15..0]
0x09 MMODE Miscellaneous Mode Register R/W [15..0]
0x0A STAGE Staging Register R/W [15..0]
0x0B IADDR Indirect Address Register R/W [31..0]
0x0C IDATA Indirect Data Register R/W [31..0]
0x0D BOOT Boot Mode Register R/W [15..0]
0x0E PLL_HI PLL Control Register - High Byte R/W [15..0]
0x0F PLL_LO PLL Control Register - Low Byte R/W [15..0]
Table 4-5. Internal Hardware Registers
INDIRECT NAME DESCRIPTION
REGISTER
ADDRESS
0xFFFF0400 PMODE1 Pixel/Video Format
0xFFFF0404 COMP_CNT_STATUS Component count
0xFFFF0408 LINE_CNT_STATUS Line count
0xFFFF040C XTOT Total Samples per line
0xFFFF0410 YTOT Total Lines per frame
0xFFFF0414 F0_START Start Line of Field 0 [F0]
0xFFFF0418 F1_START Start Line of Field 1 [F1]
0xFFFF041C V0_START Start of active video Field 0 [F0]
0xFFFF0420 V1_START Start of active video Field 1 [F1]
0xFFFF0424 V0_END End of active video Field 0 [F0]
0xFFFF0428 V1_END End of active video Field 1 [F1]
0xFFFF042C PIXEL_START Horizontal start of active video
0xFFFF0430 PIXEL_END Horizontal end of active video
0xFFFF0440 MS_CNT_DEL Master/Slave Delay
0xFFFF0444 Reserved Reserved
0xFFFF0448 PMODE2 Pixel Mode 2
0xFFFF044C VMODE Video Mode
0xFFFF1408 EDMOD0 External DMA mode register 0
0xFFFF140C EDMOD1 External DMA mode register 1
0xFFFF1410 FFTHRP FIFO Threshold for Pixel FIFO
0xFFFF1414 Reserved Reserved
0xFFFF1418 Reserved Reserved
0xFFFF141C FFTHRC FIFO Threshold for Code FIFO
0xFFFF1420 FFTHRA FIFO Threshold for ATTR FIFO
0xFFFF1424 Reserved Reserved
0xFFFF1428 Reserved Reserved
0xFFFF142C Reserved Reserved
0xFFFF1430 Reserved Reserved
0xFFFF1434- Reserved Reserved
0xFFFF14F3
0xFFFF14F4 HWREV Hardware Revision Register
Indirect Registers:
External DMA This Section describes the ADV202’s interface to DMA. These registers
are required to be programmed by the external host processor, when used
for compressed data transfers or for pixel data/ compressed data transfers
in HIPI mode. Alternatively Normal Host mode accesses in conjunction
with the Threshold registers can be used for compressed data transfers
which does not require programming of the EDMOD registers.
.
EDMOD Register Descriptions EDMOD0 and EDMOD1 registers configure the ADV202 for external
DMA operation. DMA allows transfers to and from memory without the
on-board processor being required to perform the transactions, as it is the
case in Normal Host mode.
The external DMA registers include settings for Single/Burst DMA,
Fly-By Mode DMA, and Dedicated Chip Select (DCS) DMA. These
registers are used in conjunction with the Bus Mode (BUSMODE) and
MMODE registers.
ADDR REGISTER NAME REGISTER R/W RESET VALUE
DESCRIPTION
0xFFFF1408 EDMOD0 External DMA Mode R/W See bit Field
The 16 bit EDMOD0 register is used to assign a data FIFO to Channel 0
and to select transfer modes.
EDMOD0 Bit Field
Bit Name Description Reset
Value
Enable external DMA channel 0 0 DMEN0 0
0=disabled
1=enabled
DMA Channel 0 Assignment 2..1 DMSEL0 ‘00’
00 = Pixel Data
01 = Compressed Data
10 = Attribute Data
11 = Reserved
5..3 DMMOD0
DMA Channel 0 mode ‘000’
000 - Dedicated Chip Select DMA mode
001 - Single transfer DREQ/DACK DMA mode
010 - Burst transfer DREQ/DACK DMA mode
011 - JDATA mode
100 - reserved
101 - Single transfer Fly-by DMA mode
110 - Burst transfer Fly-by DMA mode
111 - reserved
8..6 DMBL0 DMA Channel 0 burst length [in number of accesses] ‘000’
000 = 8 - not available for DWIDTH of 8-bit
001 = 16 - for DWIDTH of 8/16 or 32-bits
010 = 32 - for DWIDTH of 8/16 or 32-bits
011 = 64 - for DWIDTH of 8/16 or 32-bits
100 = 128 - for DWIDTH of 8/16 or 32-bits
110 = 512 - for DWIDTH of 8/16-bit, for 32-bits,
not recommended
111 - 1024 - for DWIDTH of 8-bit;
not recommended for 16 bit host,
not available for 32 bit hostslable.
0
9 DR0POL
FSRQ0 / VALID polarity
0 = Active Low
1 = Active High
0
10 DA0POL
FCS0 / HOLD polarity
0 = Active Low
1 = Active High
14..11 DR0PULS DREQ0 pulse width [in Jclkcycles] ‘0001’
If DR0PULS==0, then DREQ0 will remain asserted
until DACK0 and RD/ in read mode or WR/ in write
mode are asserted.
15 Reserved Reserved for future use. Always write 0. 0
32 bit Host Interface Settings16-bit 0xFFFF0000 - DWIDTH = IWIDTH = Example: Write 0x0802 to the //
写入间接寄存器的数据16位为0x0802Indirect 0xFFFF14C0 32 bits 32 bits EDMOD0 register
Register HWIDTH = IAUTOSTP (0xFFFF1408)
32 bits = 32 bits
Sequence:
1) Write 0xFFFF1408 to the
IADDR register
2) Write 0x08020000 to the //
需要将数据放入有效的高16位传递给adv202控制器. IDATA register
Example: Read the EDMOD0
register (0xFFFF1408)
Sequence:
1) Write 0xFFFF1408 to the
IADDR register
2) Read the IDATA register
(value should be 08020000
from previous write)
Note: (HDATA[15..0]) bits
are ignored on Indirect writes.
Indirect Registers are 16-bits
aligned on 32-bit boundaries
utilizing the [31.15] byte
lanes.
Decode Slave Mode In decode slave mode video output is synchronized to the incoming HVF
signals. In both cases, XTOT, YTOT, V0_START, V1_START, V0_END,
V1_END, PIXEL_START, PIXEL_END must reflect the video standard of
the input. The part synchronizes itself to the incoming sync signals. Fields
are identified by the incoming FIELD signal.
Decode Master VSYNC, HSYNC, FIELD, or alternatively EAV/SAV codes, are generated
according to the register settings of: XTOT, YTOT, F0_START,
F1_START, V0_START, V1_START, V0_END, V1_END,
PIXEL_START, PIXEL_END.
To enable the generation of these timing signals in decode mode, VMODE register must be programmed to decode master mode and MP_656 must be set to 1 for HVF generation or 0 for EAV/SAV insertion into the video output stream .EAV/SAV mode The ADV202 can accept video with embedded EAV/SAV codes where the
YCbCr data is interleaved onto a single bus. This is setup by the user in the
firmware parameters.
DMA Mode - Dedicated Chip Select DMA Mode This mode is available for devices which use the level-sensitive logic to
monitor the FSRQx signals (as opposed to edge-triggered logic). The
FSRQx (DREQx) pins will be asserted when data/space is available in the
selected FIFO and will be de-asserted when the FIFO is empty/full. The
FCSx (DACKx) pins are used as FIFO Chip Select signals and should be
asserted in conjunction with the RD/WE pins. This mode is enabled via the
EDMOD0/EDMOD1 registers. The FSRQx/ polarities can be programmed
via the EDMOD0/EDMOD1 registers.
A programming example for DCS mode can be found in the “Getting
Started with the ADV202” programming guide.
Burst Transfer - DREQ/DACK DMA In this mode, the ADV202 will assert DREQx when there is at least one
burst data transfer available for the assigned FIFO. In encode mode, the
DREQx assertion indicates that output data is present in the FIFO. In
decode mode, this indicates that space is available in the FIFO for at least
one burst data transfer. The external device must respond with DACKx, in
conjunction with RD/WE/HDATA activity.
In Burst Transfer Fly-By Mode, the functionality of the RD and WE
pins is reversed.
DREQ/DACK DMA Mode• DREQ/ is asserted by the ADV202 whenever data is ready
• No FIFO threshold programming required
• Maximum data throughput = 200 Mbps (burst)
DCS DMA Mode• Hardwired directly from the FIFOs
• FIFO thresholds must be programmed by the user
• Maximum data throughput = 200 Mbps
