• Direct connection to three processor Local Bus
types
• M Mode—Motorola MPC850 and MPC860,
IBM PowerPC 801
• C Mode (non-multiplexed address/data)—
Intel i960, DSPs, custom ASICs and FPGAs,
and others
• J Mode (multiplexed address/data)—
Intel i960, IBM PowerPC 401, DSPs,
and others
• Asynchronous clock inputs for PCI and
Local Buses
Three Data Transfer modes—Direct Master,
Direct Slave, and DMA
2.2.2 Direct Master 2.2.4.1 Local Bus Wait States
Local Bus cycles can be single or Burst cycles. As a In Direct Master mode, when accessing the PCI 9656
Local Bus target, the PCI 9656 allows access to the registers or transferring data, the PCI 9656 is a Local
PCI 9656 internal registers and the PCI Bus. Bus slave. As a Local Bus slave, the PCI 9656 inserts
external wait states with the TA# signal.
Local Bus Direct Master accesses to the PCI 9656
must be for a 32-bit non-pipelined bus. Non-32-bit In Direct Slave and DMA modes, the PCI 9656 acts as
Direct Master accesses to the PCI 9656 require simple a Local Bus master. When TA# input is disabled, the
external logic (latch array to combine data into a Internal Wait State Counter(s) can be used to program
32-bit bus). the number of internal wait states between the first
address-to-data state, and subsequent data-to-data in
2.2.3 Direct Slave Burst mode. (Refer to Table 2-7.)
The PCI Bus Master reads from and writes to the
Local Bus (the PCI 9656 is a PCI Bus target and a
Local Bus master).
4.2.5.1 Single Cycle Mode
Single Cycle mode is the default Data Transfer mode.
In Single Cycle mode, the PCI 9656 issues one ADS#
per data cycle. The starting address for a single cycle
Data transfer can be on any address.
For single cycle Data transfers, Burst mode is disabled
(LBRD0[24]=0 for Space 0, LBRD1[8]=0 for Space 1,
LBRD0[26]=0 for Expansion ROM, and/or
DMAMODEx[8]=0 for Channel x). For a 32-bit Local
Bus, if a starting address in a Direct Slave or DMA
PCI-to-Local transfer is not aligned to an Lword
boundary, the PCI 9656 performs a single cycle until
the next Lword boundary.
4.2.5 Data Transfer Modes
The PCI 9656 supports C and J modes with three
Data Transfer modes:
• Single Cycle
• Burst-4
• Continuous Burst
Single Cycle mode is the default Data Transfer mode,
Burst-4 mode is C and J mode-compatible, and
Continuous Burst mode provides the highest
throughput.
4.2.5.3 Continuous Burst Mode
Continuous Burst mode enables the PCI 9656 to
perform data bursts of longer than four data. However,
special external interface devices are required that
can accept bursts longer than four data.
5.4 DIRECT DATA TRANSFER MODES
In C and J modes, the PCI 9656 supports three Direct
Data Transfer modes:
• Direct Master—Local CPU accesses PCI memory
or I/O
• Direct Slave—PCI Master accesses Local memory
or I/O
• DMA—PCI 9656 DMA Controller(s) reads/writes
PCI memory to/from Local memory
All three Direct Data Transfer modes generate dummy
cycles. The PCI 9656 generates dummy cycles on the
PCI and Local Buses. The PCI Bus C/BE[7:0]# pins
and the Local Bus LBE[3:0]# pins must be monitored
so that dummy cycles can be recognized on either
bus.
5.4.4 DMA Operation
The PCI 9656 supports two independent DMA
channels capable of transferring data from the PCI-to-Local Bus
and Local-to-PCI Bus.
Each channel consists of a DMA Controller and a
dedicated bi-directional FIFO. Both channels support
DMA Block, Scatter/Gather, and Demand Mode
transfers, with or without End of Transfer (EOT#).
Master mode must be enabled (PCICR[2]=1) before
the PCI 9656 can become a PCI Bus master. In
addition, both DMA channels can be programmed to:
• Operate with 8-, 16-, or 32-bit Local Bus data
widths
• Use zero to 15 internal wait states (Local Bus)
• Enable/disable external wait states (Local Bus)
• Enable/disable Local Bus burst capability
• Set Local Bus mode (refer to Table 5-6)
• Hold Local address constant (Local Slave is FIFO)
or incremented
• Perform PCI Memory Write and Invalidate
(command code = Fh) or normal PCI Memory Write
(command code = 7h)
• Stop/pause Local transfer with or without BLAST#
(DMA Fast/Slow Terminate mode)
• Operate in DMA Clear Count mode
With End of Transfer (EOT), an EOT# signal is
asserted to the I/O accelerator to end the transfer.
When EOT# is asserted, the I/O accelerator
immediately aborts the current DMA transfer
With DMA Demand mode, a hardware DREQx#/
DACKx# signal pair is used to pause and resume the
DMA transfer.
The PCI 9656 is a PCI Bus Master interface chip that
connects a 64-bit, 66 MHz PCI Bus to one of three
32-bit, 66 MHz Local Bus types.
Big/Little Endian Conversion. Supports dynamic
switching between Big Endian (Address Invariance)
and Little Endian (Data Invariance) operations for
Direct Slave, Direct Master, DMA, and internal
Register accesses on the Local Bus.
Direct Master. Supports PCI accesses from a Local
Bus master. Burst transfers are supported for
memory-mapped devices. Single transfers are
supported for memory-mapped and I/O devices.
Direct Slave. Supports Burst Memory-Mapped and
single I/O-Mapped accesses to the Local Bus
Supports 8-, 16-, and 32-bit Local Bus Data transfers.
The Read and Write FIFOs enable high-performance
bursting.
Three PCI-to-Local Address Spaces. Supports three
PCI-to-Local Address spaces in Direct Slave mode—
Space 0, Space 1, and Expansion ROM. These
spaces allow any PCI Bus master to access the Local
Bus Memory spaces with programmable wait states,
bus data width, burst capabilities, and so forth.
// 总线预取
Direct Master and Direct Slave Read Ahead Mode.
Supports Read Ahead mode, where prefetched data
can be read from the internal Read FIFO instead of the
external bus. The address must be subsequent to the
previous address and 32-bit-aligned. This feature
allows for increased bandwidth utilization through
reduced data latency.
Two DMA Channels with Independent FIFOs.
Provides two independently programmable DMA
Controllers with independently programmable FIFOs.
Each channel supports DMA Block and Scatter/Gather
modes, including DMA Ring Management (Valid
mode), as well as EOT and DMA Demand modes.
Serial EEPROM Interface. Includes an optional serial
EEPROM interface that can be used to load
configuration information. This is useful for loading
information unique to a particular adapter, such as the
Device or Vendor ID, especially in designs that do not
include a Local processor.
2.1.2 PCI Master Command Codes
The PCI 9656 becomes the PCI Bus Master
to perform DMA or Direct Master transfers. The
PCI command code used by the PCI 9656 during a
Direct Master or DMA transfer is specified by the
2.1.1 Direct Slave Command Codes
value(s) contained in the CNTRL[15:0] register bits.
As a target, the PCI 9656 allows access to the Except when in Memory Write and Invalidate
PCI 9656 internal registers and Local Bus, using the (MWI) mode (PCICR[4]=1; DMPBAM[9]=1 or
commands listed in Table 2-1. DMAMODEx[13]=1; PCICLSR[7:0] = cache line size of
8 or 16 Lwords). In MWI mode for a Direct Master or
All Direct Slave Read or Write accesses to the
DMA transfer, if the starting address alignment is
PCI 9656 can be Byte (8-bit), Word (16-bit), Lword
aligned with the cache line size and upon determining
(32-bit), or Qword (64-bit) accesses. All memory
it can transfer at least one cache line of data, the
commands are aliased to basic memory commands.
PCI 9656 uses a PCI command code of Fh regardless
All I/O accesses to the PCI 9656 are decoded to an
of the value(s) contained in the CNTRL[15:0] register
Lword boundary. The PCI Byte Enables (C/BE[7:0]#)
bits.
are used to determine which bytes are read or written.
An I/O access with illegal Byte Enable combinations is
terminated with a Target Abort. All Configuration
register Read or Write accesses to the PCI 9656 can
be Byte, Word, or Lword accesses, with Byte Enables
used to determine which bytes are read or written.
2.1.3 PCI Arbitration
The PCI 9656 asserts REQ# to request the PCI Bus.
The PCI 9656 can be programmed using the PCI
Request Mode bit (MARBR[23]) to de-assert REQ#
when the PCI 9656 asserts FRAME# during a Bus
Master cycle, or to hold REQ# asserted for the entire
Bus Master cycle. The PCI 9656 always de-asserts
REQ# for a minimum of two PCI clocks between Bus
Master ownership that includes a Target disconnect.
During a Direct Master Write cycle, the PCI 9656 PCI
REQ# assertion can be delayed by programming the
Direct Master Delayed Write Mode bits (DMPBAM
[15:14]). DMPBAM can be programmed to wait 0, 4, 8,
or 16 PCI Bus clocks after the PCI 9656 has received
its first Write data from the Local Bus Master and is
ready to begin the PCI Write transaction. This function
is useful in applications where a Local master is
bursting and a Local Bus clock is slower than the
PCI Bus clock. This allows Write data to accumulate in
the PCI 9656 Direct Master Write FIFO, which
provides for better use of the PCI Bus.
The PCI 9656 interfaces a PCI Host Bus to several
Local Bus types, as listed in Table 2-6. It operates in
one of three modes—M, C, and J, selected through
the MODE[1:0] pins—corresponding to the three bus
types.
Direct Slave Accesses to 8- or 16-Bit Local Bus
Direct PCI access to an 8- or 16-bit Local Bus results
in the PCI Bus Lword/Qword being broken into
multiple Local Bus transfers. For each transfer, Byte
Enables are encoded to provide Transfer Size bits(TSIZ[0:1]).
PCI 9656 Initialization from Serial EEPROM
After reset, the PCI 9656 attempts to read the serial
EEPROM to determine its presence. A first-returned
bit set to 0 indicates a serial EEPROM is present. The
first word is then checked to verify that the serial
EEPROM is programmed. If the first word (16 bits) is
all ones (1), a blank serial EEPROM is present. If the
first word (16 bits) is all zeros (0), no serial EEPROM
is present. For both conditions, the PCI 9656 reverts to
the default values. (Refer to Table 2-12.) The Serial
EEPROM Present bit is set (CNTRL[28]=1) if the serial
EEPROM is detected as present and is programmed or blank.
In C and J modes, the PCI 9656 supports three Direct
Data Transfer modes:
• Direct Master—Local CPU accesses PCI memory or I/O
• Direct Slave—PCI Master accesses Local memory or I/O
• DMA—PCI 9656 DMA Controller(s) reads/writes
PCI memory to/from Local memory
5.4 DIRECT DATA TRANSFER MODES 5.4.1.1 Direct Master Memory
and I/O Decode
In C and J modes, the PCI 9656 supports three Direct
Data Transfer modes: The Range register and the Local Base Address
specify the Local Address bits to use for decoding
• Direct Master—Local CPU accesses PCI memory
a Local-to-PCI access (Direct Master). The Memory or
or I/O
I/O space range must be a power of 2 and the Range
• Direct Slave—PCI Master accesses Local memory
register value must be two’s complement of the range
or I/O
value. In addition, the Local Base Address must be a
• DMA—PCI 9656 DMA Controller(s) reads/writes
multiple of the range value
PCI memory to/from Local memory
1.2.1.2.1 DMA Block Mode
DMA Block mode is the simplest DMA mode. The
Master simply programs the description of a single
transfer in the I/O accelerator and sets the Start bit(s)
(DMACSRx[1]=1). The I/O accelerator signals DMA
completion to the Master, either by setting a Done bit
in one of its registers that the Master polls
(DMACSRx[4]) or by asserting an interrupt.
Register 11-83. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Reset
Bit Description Read Write
DMA Channel 0 Enable. Writing 1 enables the channel to transfer data.
0 Writing 0 disables the channel from starting a DMA transfer, and if in the Yes Yes 0
process of transferring data, suspends the transfer (pause).
DMA Channel 0 Start. Writing 1 causes the channel to start transferring data
1 No Yes/Set 0
if the channel is enabled.
DMA Channel 0 Abort. Writing 1 causes the channel to abort the current
transfer. The DMA Channel 0 Enable bit must be cleared (DMACSR0[0]=0).
2 No Yes/Set 0
Sets the DMA Channel 0 Done bit (DMACSR0[4]=1) when the abort is
complete.
3 DMA Channel 0 Clear Interrupt. Writing 1 clears DMA Channel 0 interrupts. No Yes/Clr 0
DMA Channel 0 Done. Reading 1 indicates the transfer is complete.
The transfer may be complete either because the DMA transfer finished
4 successfully, or that the DMA transfer was aborted when software set the Yes No
Abort bit (DMACSR0[2]=1). Reading 0 indicates the Channel transfer is not
complete.
Register 11-77. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer
Reset
Bit Description Read Write
DMA Channel 0 Descriptor Location. Writing 1 indicates PCI Address
0 Yes Yes 0
space. Writing 0 indicates Local Address space.
DMA Channel 0 End of Chain. Writing 1 indicates end of chain. Writing 0
1 Yes Yes 0
indicates not end of chain descriptor. (Same as DMA Block mode.)
DMA Channel 0 Interrupt after Terminal Count. Writing 1 causes an
2 interrupt to be asserted after the terminal count for this descriptor is reached. Yes Yes 0
Writing 0 disables interrupts from being asserted.
DMA Channel 0 Direction of Transfer. Writing 1 indicates transfers from
3 the Local Bus to the PCI Bus. Writing 0 indicates transfers from the PCI Bus Yes Yes 0
11—Registers
to the Local Bus.
DMA Channel 0 Next Descriptor Address. Qword-aligned
Yes Yes 0h
31:4
(DMADPR0[3:0]=0h).
5.4.4.2 DMA Block Mode
The Host processor or the Local processor sets the
PCI and Local starting addresses, transfer byte count,
and transfer direction. The Host or Local processor
then sets the DMA Channel Start and Enable bits
(DMACSRx[1:0]=11b) to initiate a transfer. The
PCI 9656 requests the PCI and Local Buses and
transfers data. Once the transfer completes, the
PCI 9656 sets the Channel Done bit(s)
(DMACSRx[4]=1) and asserts an interrupt(s)
(INTCSR[16], INTCSR[8], DMAMODEx[17], and/or
DMAMODEx[10]) to the Local processor or the PCI
Host (programmable). The Channel Done bit(s) can be
polled, instead of interrupt generation, to indicate the
DMA transfer status.
DMA registers are accessible from the PCI and Local
Buses. (Refer to Figure 5-12.)
During DMA transfers, the PCI 9656 is a master on
both the PCI and Local Buses. For simultaneous
access, Direct Slave or Direct Master has a higher
priority than DMA.
The PCI 9656 releases the PCI Bus, if one of the
following conditions occur (refer to Figures 5-13
and 5-14):
• FIFO is full (PCI-to-Local Bus)
• FIFO is empty (Local-to-PCI Bus)
• Terminal count is reached
• PCI Bus Latency Timer expires (PCILTR[7:0])—
normally programmed by the Host PCI BIOS
according to the PCI Maximum Latency
(PCIMLR) register value—and PCI GNT#
is de-asserted
• PCI Target asserts STOP#
The PCI 9656 releases the Local Bus, if one of the
following conditions occurs:
• FIFO is empty (PCI-to-Local Bus)
• FIFO is full (Local-to-PCI Bus)
• Terminal count is reached
• Local Bus Latency Timer is enabled
(MARBR[16]=1) and expires (MARBR[7:0])
• BREQi is asserted
• Direct Slave request is pending
5.4.4.3 DMA Scatter/Gather Mode
In DMA Scatter/Gather mode, the Host processor or
Local processor sets up descriptor blocks in PCI or
Local memory composed of PCI and Local addresses,
transfer count, transfer direction, and address of the
next descriptor block. (Refer to Figures 5-15 and
5-16.) The Host or Local processor then:
• Enables the DMA Scatter/Gather mode bit(s)
(DMAMODEx[9]=1)
• Sets up the address of initial descriptor block
in the PCI 9656 Descriptor Pointer register(s)
(DMADPRx)
• Initiates the transfer by setting a control bit(s)
(DMACSRx[1:0]=11b)
The PCI 9656 supports zero wait state Descriptor
Block bursts from the Local Bus when the Local Burst
Enable bit(s) is enabled (DMAMODEx[8]=1).
The PCI 9656 loads the first descriptor block and
initiates the Data transfer. The PCI 9656 continues to
load descriptor blocks and transfer data until it detects
the End of Chain bit(s) is set (DMADPRx[1]=1). When
the End of Chain bit(s) is detected, the PCI 9656
completes the current descriptor block, sets the DMA
Done bit(s) (DMACSRx[4]=1), and asserts a PCI or
Local interrupt (INTA# or LINTo#, respectively), if the
interrupt is enabled (DMAMODEx[10]=1).
The PCI 9656 can also be programmed to assert PCI
or Local interrupts after each descriptor is loaded, then
the corresponding Data transfer is finished.
The DMA Controller(s) can be programmed to clear
the transfer size at completion of each DMA transfer,
using the DMA Clear Count Mode bit(s) (DMAMODEx
[16]=1).
5.4.4.3.3 DMA Ring Management (Valid Mode)
In DMA Scatter/Gather mode, when the Ring
Management Valid Mode Enable bit(s) is set to 0
(DMAMODEx[20]=0), the Valid bit(s) [bit(s) 31 of
transfer count] is ignored. When the Ring
Management Valid Mode Enable bit(s) is set to 1
(DMAMODEx[20]=1), the DMA descriptor proceeds
only when the Ring Management Valid bit(s) is set
(DMASIZx[31]=1). If the Valid bit(s) is set, the transfer
count is 0, and the descriptor is not the last descriptor,
then the DMA Controller(s) moves on to the next
descriptor in the chain.
When the Ring Management Valid Stop Control bit(s)
is set to 0 (DMAMODEx[21]=0), the DMA Scatter/
Gather controller continuously polls the descriptor with
the Valid bit(s) set to 0 (invalid descriptor) until the
Valid bit(s) is read as 1, which initiates the DMA
transfer. When the Valid bit(s) is read as 1, the DMA
transfer begins. When the Ring Management Valid
Stop Control bit(s) is set to 1 (DMAMODEx[21]=1), the
DMA Scatter/Gather controller pauses if a Valid bit(s)
with a value of 0 is detected. In this case, the
processor must restart the DMA Controller(s) by
setting the DMA Channel Start bit(s)
(DMACSRx[1]=1). The DMA Clear Count mode bit(s)
must be enabled (DMAMODEx[16]=1) for the Ring
Management Valid bit(s) (DMASIZx[31]) to be cleared
at the completion of each descriptor. (Refer to
Figure 5-19 and/or Figure 5-20 for the DMA Ring
Management descriptor load sequence for SAC and
DAC PCI addresses.)
5.4.4.6 DMA Channel Priority
The DMA Channel Priority bits (MARBR[20:19]) can
be used to specify the priorities listed in Table 5-7.
Table 5-7. DMA Channel Priority Bit Specifications
MARBR[20:19] Channel Priority
00b Rotating
01b DMA Channel 0
10b DMA Channel 1
11b Reserved
5.4.4.7 DMA Channel x Interrupts
A DMA channel can assert a PCI or Local interrupt
when done (transfer complete) or after a transfer is
complete for the current descriptor in DMA Scatter/
Gather mode. The DMA Channel Interrupt Select bit(s)
determine whether to assert a PCI or Local interrupt
(DMAMODEx[17]=1 or 0, respectively). The PCI or
Local processor can read the DMA Channel Interrupt
Active bit(s) to determine whether a DMA Channel
interrupt is pending (INTCSR[22 and/or 21]=1).
The DMA Channel Done bit(s) (DMACSRx[4]) can be
used to determine whether an interrupt is one of the
following:
• DMA Done interrupt
• Transfer complete for current descriptor interrupt
Setting DMAMODEx[10]=1 enables a DMA Channel
Done interrupt. In DMA Scatter/Gather mode, the
Descriptor Pointer register Interrupt after Terminal
Count bit(s) (DMADPRx[2], loaded from Local
memory) specifies whether to assert an interrupt at the
end of the transfer for the current descriptor.
Setting DMACSRx[3]=1 clears a DMA Channel
interrupt.
5.4.4.13 Local Bus DMA Priority
The PCI 9656 supports programmable Local Bus
arbitration priority for DMA Channel 0 and Channel 1,
when both channels are active (priority set with
MARBR[20:19]). DMA Block and Scatter/Gather
modes have priority over DMA Demand mode. DMA DMA Demand mode产生priority调度[luther.gliethttp 2009年10月11日]
transfer direction does not influence DMA channel
priority.
There are three types of priorities:
• Channel 0 Priority—DMA Channel 0 completes
the transfer on the Local Bus before Channel 1.
If Channel 1 is performing a Data transfer, with
Channel 0 set as highest priority and started,
Channel 1 continues its transfer until the Local 直到dma1传输完成或者被中断了,才会执行优先级更高的dma0传输,如果dma0传输开始,那么将永远不会调度到dma1,直到dma0传输完毕为止,dma1才可以获得总线继续传输[luther.gliethttp 2009年10月11日].
Bus Latency Timer (MARBR[7:0]) expires,
preempted by a Direct Slave Data transfer, or
another termination occurs (EOT# assertion,
DREQx# de-assertion, or BREQi# assertion).
Channel 0 then owns the Local Bus until transfer 看来dma是独占通道的,直到发送完毕,block模式就要全部发送完毕,sg模式则2个dma可以交替lhold获取local bus总线权.
但是adv202因为并不会一次传输完所有数据,所以dma1会释放总线,之后dma0就又会开始执行传输
因为他的优先级高,所以可以设置为下面的的Rotational方式[luther.gliethttp 2009年10月11日].
completion, before Channel 1 can continue the
interrupted transfer, unless Channel 1 previously
completed its transfer.
• Channel 1 Priority—DMA Channel 1 completes
its transfer on the Local Bus before Channel 0.
If Channel 0 is performing a Data transfer, with
Channel 1 set as highest priority and started,
Channel 0 continues its transfer until the
Local Bus Latency Timer expires, preempted
by a Direct Slave Data transfer, or another
termination occurs (EOT# assertion,
DREQx# de-assertion, or BREQi# assertion).
Channel 1 then owns the Local Bus until
transfer completion, before Channel 0 can
continue the interrupted transfer, unless
Channel 0 previously completed its transfer.
• Rotational Priority—Depends on the transfer 交替执行dma0和dma1传输,直到BREQi# assertion或EOT# assertion或DREQx# de-assertion发生,将执行交替替换[luther.gliethttp 2009年10月11日]
direction, however, if the starting bus is the same
for both DMA channels, in the freshly started DMA,
Channel 0 always starts first. Rotational priority
does not start unless the ongoing DMA channel
Data transfer is interrupted by the Local Bus
Latency Timer expiration, preempted by a
Direct Slave Data transfer, or another termination
occurs (EOT# assertion, DREQx# de-assertion, or
BREQi# assertion). The other DMA channel then
owns the Local Bus until the previously described
interrupts or terminations occur. Rotational priority
occurs each time a DMA channel loses Local Bus
ownership, unless one of the DMA channels
previously completed its transfer.
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