Vivado - Constraints tutorial学习

Overview
XDC 是Synopsys Design Contstraints 和 Xilinx专有约束的集合。

XDC 还是TCL 命令

Vivado Design Suite synthesis and implementation tools  are timing driver.

1) 方法一： 通过添加constrain 文件来添加

Open Synthesized Design --> Edit Timing Constraints


2) 方法二


Vivado Design Analysis and Closure Techniques Tutorial

steps:
pre-implementation design and analysis capabilities
Implementation exploration features
Floorplanning implementation results

-- Analyze device utilization statistics to target alternate devices and choose the optimal device
-- run design rule checks to quickly resolve constraint conflicts that would otherwise cause implementation errors
--use the netlist,logic hierarchy and schematic windows to explore logic
--perform a quick estimation of timing performance to assess design feasibility and identify potential problem areas 
--view modify or create constraints in the design
--analyze the design hierarchical connectivity and data flow as well as identify critical logic connectivity and clock domains 
--floorplan timing-critical logic to improve timing and data flow.
--view routing resouces in the detailed device window