分类： 嵌入式
2010-05-26 11:10:58
"三段式"状态机的 Verilog HDL 代码模板如下：
//状态调转
always @(posedge clk) begin
if (!rst_n)
state <= idle;
else
state <= next_state;
end
//下一状态的计算
always @(state) begin
case(state)
s0: next_state = ;
s1: next_state = ;
...
endcase
end
//输出逻辑的处理
always @(posedge clk) begin
case(state)
s0: begin
out1 <= ;
out2 <= ;
...
end
s1: begin
out1 <= ;
out2 <= ;
...
end
...
endcase
end
