UCC配置:
The QUICC Engine block UCC implement a wide range of protocols and interfaces.
The Quick Engine block can be configured to implement different protocols concurrently by configuring each UCC to run a different protocol as needed by the target application.
Before the UCC is configured for protocol-specific operation, it should be set to either fast or slow protocols mode through the general UCC extended mode register (GUEMR). This should be done as the first stage of the initialization process.
The GUMR mode defines the programming model for the UCC.
内存映射问题：
在物理地址为0xFF40_0000（FLASH）里，有一块2M的空间，存放着系统基本上所有配置的寄存器。
首先开始的512字节存放的是系统配置寄存器，其中包含了所有内存映射寄存器（local bus；ddr；pci等主要11个window的基址和窗口大小）的值。再接下来是看门狗寄存器，实时时钟寄存器，...QUICC Engine等控制寄存器。
复位问题：
三种复位：
1.上电复位：重置整个器件，包括时钟逻辑和错误捕捉寄存器
2.硬复位：重置整个器件，不包括时钟逻辑和错误捕捉寄存器
3.软复位：初始化内部逻辑，但保持系统配置。
由外部ctg_reset_source[0-2]选择复位类型。
在reset configuration word控制着时钟分频，和其他的器件功能例如是处于PCI host还是agent工作模式，也控制处理器的boot location和大小端模式。
当系统上电复位或者硬复位时，reset configuration word可以从local bus或者I2C接口装入。通过reset control word high register中的BMS为来控制，
当它的值为0时： Boot memory space is 8 Mbytes at 0x0000_0000 to 0x007F_FFFF.
e300 core register MSR[IP] initial value is 0b0.
The core, if enabled to boot, begins fetching boot code from address 0x0000_0100
and exceptions are vectored to the physical address of 0x000n_nnnn.
当它的值为1时：Boot memory space is 8 Mbytes at 0xFF80_0000 to 0xFFFF_FFFF.
e300 core register MSR[IP] initial value is 0b1.
The core, if enabled to boot, begins fetching boot code from address 0xFFF0_0100
and exceptions are vectored to the physical address of 0xFFFn_nnnn.
当从local bus eeprom装入时，即选中了LCS0的rom，因为rom的位数不明，所以，cpu从rom里一个字节一个字节的读取数据。
当从local bus装入复位控制字时，用到LA[27-31]而不是LAD[27-31],所以接FLASH应接的是LA。
if the HRCW is loaded through the local bus,
the LA[27:31 pins are used and not the LAD[27:31] pins. The LAD[27:31 pins are not driven during HRCW loading.only the LA[27:31] are shown incrementing
during the load of the HRCW.Out of reset, the LA[27:31] and LAD[27:31] mirror each
other (while LALE is asserted).
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