2017年(9)
分类: 嵌入式
2017-11-08 20:19:00
seq. | Name | Brief | Actual Code | Space/Time | Description |
1 | abs Rd, Rs | Absolute Value |
addu Rd, $0, Rs bgez Rs, 1 sub Rd, $0, Rs |
3/3 |
|
2 | beqz Rs, Label | Branch if Equal to Zero | beq Rs, $0, Label | 1/1 |
|
3 | bge Rs, Rt, Label | Branch if Greater than or Equal |
slt $at, Rs, Rt 2/2 beq $at, $0, Label |
2/2 |
If Reg.File[Rs] > = Reg.File[Rt] branch to Label Used to compare values represented in the two's complement number system. |
4 | bgeu Rs, Rt, Label | Branch if Greater than or Equal Unsigned |
sltu $at, Rs, Rt beq $at, $0, Label |
2/2 |
If Reg.File[Rs] > = Reg.File[Rt] branch to Label Used to compare addresses (unsigned values). |
5 | bgt Rs, Rt, Label | Branch if Greater Than |
slt $at, Rt, Rs bne $at, $0, Label |
2/2 |
If Reg.File[Rs] > Reg.File[Rt] branch to Label Used to compare values represented in the two's complement number system. |
6 | bgtu Rs, Rt, Label | Branch if Greater Than Unsigned |
sltu $at, Rt, Rs bne $at, $0, Label |
2/2 |
If Reg.File[Rs] > Reg.File[Rt] branch to Label Used to compare addresses (unsigned values). |
7 | ble Rs, Rt, Label | Branch if Less Than or Equal |
slt $at, Rt, Rs beq $at, $0, Label |
2/2 |
If Reg.File[Rs] < = Reg.File[Rt] branch to Label Used to compare values represented in the two's complement number system. |
8 | bleu Rs, Rt, Label | Branch if Less Than or Equal Unsigned |
sltu $at, Rt, Rs beq $at, $0, Label |
2/2 |
If Reg.File[Rs] < = Reg.File[Rt] branch to Label Used to compare addresses (unsigned values). |
9 | blt Rs, Rt, Label | Branch if Less Than |
slt $at, Rs, Rt bne $at, $0, Label |
2/2 |
If Reg.File[Rs] < Reg.File[Rt] branch to Label Used to compare values represented in the two's complement number system |
10 | bltu Rs, Rt, Label | Branch if Less Than Unsigned |
sltu $at, Rs, Rt bne $at, $0, Label |
2/2 |
If Reg.File[Rs] < Reg.File[Rt] branch to Label Used to compare addresses (unsigned values). |
11 | bnez Rs, Label | Branch if Not Equal to Zero | bne Rs, $0, Label | 1/1 |
|
12 | b Label | Branch Unconditional | bgez $0, Label | 1/1 |
|
13 | div Rd, Rs, Rt | Divide |
bne Rt, $0, ok break $0 ok: div Rs, Rt mflo Rd |
4/41 |
|
14 | divu Rd, Rs, Rt | Divide Unsigned |
bne Rt, $0, ok break $0 ok: divu Rs, Rt mflo Rd |
4/41 |
|
15 | la Rd, Label | Load Address |
lui $at, Upper 16-bits of Label ori Rd, $at, Lower 16-bits of Label |
2/2 |
Used to initialize pointers |
16 | li Rd, value | Load Immediate |
lui $at, Upper 16-bits of value ori Rd, $at, Lower 16-bits of value |
2/2 | Initialize registers with negative constants and values greater than 32767. |
17 | li Rd, value | Load Immediate | ori Rt, $0, value | 1/1 | Initialize registers with positive constants less than 32768. |
18 | move Rd, Rs | Move | addu Rd, $0, Rs | 1/1 |
|
19 | mul Rd, Rs, Rt | Multiply |
mult Rs, Rt mflo Rd |
2/33 |
|
20 | mulo Rd, Rs, Rt | Multiply (with overflow exception) |
mult Rs, Rt mfhi $at mflo Rd sra Rd, Rd, 31 beq $at, Rd, ok break $0 ok: mflo Rd |
7/37 |
|
21 | mulou Rd, Rs, Rt | Multiply Unsigned (with overflow exception) |
multu Rs, Rt mfhi $at beq $at, $0, ok ok: break $0 mflo Rd |
5/35 |
|
22 | neg Rd, Rs | Negate | sub Rd, $0, Rs | 1/1 |
Two's complement negation. An exception is generated when there is an attempt to negate the most negative value: 2,147,483,648. |
23 | negu Rd, Rs | Negate Unsigned | subu Rd, $0, Rs | 1/1 |
|
24 | nop | Nop | or $0, $0, $0 | 1/1 |
|
25 | not Rd, Rs | Not | nor Rd, Rs, $0 | 1/1 | A bit-wise Boolean complement. |
26 | rem Rd, Rs, Rt | Remainder |
bne Rt, $0, 8 break $0 div Rs, Rt mfhi Rd |
4/40 |
|
27 | remu Rd, Rs, Rt | Remainder Unsigned |
bne Rt, $0, ok break $0 ok: divu Rs, Rt mfhi Rd |
4/40 |
|
28 | rol Rd, Rs, Rt | Rotate Left Variable |
subu $at, $0, Rt srlv $at, Rs, $at sllv Rd, Rs, Rt or Rd, Rd, $at |
4/4 | The lower 5-bits in Rt specifys the shift amount. |
29 | ror Rd, Rs, Rt | Rotate Right Variable |
subu $at, $0, Rt sllv $at, Rs, $at srlv Rd, Rs, Rt or Rd, Rd, $at |
4/4 |
|
30 | rol Rd, Rs, sa | Rotate Left Constant |
srl $at, Rs, 32-sa sll Rd, Rs, sa or Rd, Rd, $at |
3/3 |
|
31 | ror Rd, Rs, sa | Rotate Right Constant |
sll $at, Rs, 32-sa srl Rd, Rs, sa or Rd, Rd, $at |
3/3 |
|
32 | seq Rd, Rs, Rt | Set if Equal |
beq Rt, Rs, yes ori Rd, $0, 0 beq $0, $0, skip yes: ori Rd, $0, 1 skip: |
4/4 |
|
33 | sge Rd, Rs, Rt | Set if Greater Than or Equal |
bne Rt, Rs, yes ori Rd, $0, 1 beq $0, $0, skip yes: slt Rd, Rt, Rs skip: |
4/4 |
|
34 | sgeu Rd, Rs, Rt | Set if Greater Than or Equal Unsigned |
bne Rt, Rs, yes ori Rd, $0, 1 beq $0, $0, skip yes: sltu Rd, Rt, Rs skip: |
4/4 |
|
35 | sgt Rd, Rs, Rt | Set if Greater Than | slt Rd, Rt, Rs | 1/1 |
|
36 | sgtu Rd, Rs, Rt | Set if Greater Than Unsigned | sltu Rd, Rt, Rs | 1/1 |
|
37 | sle Rd, Rs, Rt | Set if Less Than or Equal |
bne Rt, Rs, yes ori Rd, $0, 1 beq $0, $0, skip yes: slt Rd, Rs, Rt skip: |
4/4 |
|
38 | sleu Rd, Rs, Rt | Set if Less Than or Equal Unsigned |
bne Rt, Rs, yes ori Rd, $0, 1 beq $0, $0, skip yes: sltu Rd, Rs, Rt skip: |
4/4 |
|
39 | sne Rd, Rs, Rt | Set if Not Equal |
beq Rt, Rs, yes ori Rd, $0, 1 beq $0, $0, skip yes: ori Rd, $0, 0 skip: |
4/4 |
|
40 | ulh Rd, 3(Rs) | Unaligned Load Halfword Unsigned |
lb Rd, 4(Rs) lbu $at, 3(Rs) sll Rd, Rd, 8 or Rd, Rd, $at |
4/4 |
|
41 | ulhu Rd, 3(Rs) | Unaligned Load Halfword |
lbu Rd, 4(Rs) lbu $at, 3(Rs) sll Rd, Rd, 8 or Rd, Rd, $at |
4/4 |
|
42 | ulw Rd, 3(Rs) | Unaligned Load Word |
lwl Rd, 6(Rs) lwr Rd, 3(Rs) |
2/2 |
|
43 | ush Rd, 3(Rs) | Unaligned Store Halfword |
sb Rd, 3(Rs) srl $at, Rd, 8 sb $at, 4(Rs) |
3/3 |
|
44 | usw Rd, 3(Rs) | Unaligned Store Word |
swl Rd, 6(Rs) swr Rd, 3(Rs) |
2/2 |
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