TQ2440裸板学习笔记4--sdram初始化

TQ2440用的内存是2片MT48LC16M16A2 4Meg x 16 x 4 bank组成32位。

从DataSheet中可以看出：MT48LC16M16A2 的

ReFresh_Count=8K 

Row_Addressing = 8K(A0-A12)

Bank_Addressing = 4(BA0-BA1)

Column_Addressing = 512(A0-A8)

一、代码

1.1 start.S

.text
.global _start
_start:
    ldr r0, =0x53000000
    mov r1, #0x0
    str r1, [r0]

#define COCKTIME    0x4C000000
#define MPLLCON        0x4C000004
#define UPLLCON        0x4C000008
#define CLKCON        0x4C00000C
#define CLKSLOW        0x4C000010
#define CLKDIVN     0x4C000014
#define CAMDIVN     0x4C000018
    /*FCLK:HCLK:PCLK=1:4:8*/
    ldr r0, =CLKDIVN
    mov r1, #0x05
    str r1, [r0]

    mrc p15, 0, r0, c1, c0, 0
    orr r0, r0, #0xc0000000
    mcr p15, 0, r0, c1, c0,0

    /*MPLL=(2*m*Fin)/(P*(1<<S)), m=(MDIV+8), p=PDIV+2 s=SDIV*/
    ldr r0, =MPLLCON
    ldr r1, =((0x5C<<12)|(0x01<<4)|(0x01))
    str r1, [r0]

    ldr r0, =0x10000
1:
    sub r0, r0, #1
    bne 1b

    /*UPLL=(m*Fin)/(P*(1<<S)), m=(MDIV+8), p=(PDIV+2), s=SDIV*/
    ldr r0, =UPLLCON
    ldr r1, =((0x10<<12)|(0x01<<4)|(0x01))
    str r1, [r0]

    ldr r0, =0x10000
1:
    sub r0, r0, #1
    bne 1b

    ldr sp, =1024*4
    bl init_sdram ;增加初始化sdram
    bl main

loop:
    b loop

1.2 sdram.c

#define BWSCON (*(volatile unsigned int *) 0x48000000)
#define BANKCON0 (*(volatile unsigned int *) 0x48000004)
#define BANKCON1 (*(volatile unsigned int *) 0x48000008)
#define BANKCON2 (*(volatile unsigned int *) 0x4800000C)
#define BANKCON3 (*(volatile unsigned int *) 0x48000010)
#define BANKCON4 (*(volatile unsigned int *) 0x48000014)
#define BANKCON5 (*(volatile unsigned int *) 0x48000018)
#define BANKCON6 (*(volatile unsigned int *) 0x4800001C)
#define BANKCON7 (*(volatile unsigned int *) 0x48000020)
#define REFRESH (*(volatile unsigned int *) 0x48000024)
#define BANKSIZE (*(volatile unsigned int *) 0x48000028)
#define MRSRB6 (*(volatile unsigned int *) 0x4800002C)
#define MRSRB7 (*(volatile unsigned int *) 0x48000030)

void init_sdram(void)
{
/* REFRESH parameter */
#define REFEN           0x1 /* Refresh enable */
#define TREFMD          0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp                 0x0
#define Trc             0x3
#define Tchr            0x2
#define REFCNT          0x4f4

    /* bank1,2-ide bk3,5,7-null bk4-dm9000 bk6-sdram*/
    BWSCON =(0x02<<24);
    BANKCON0 = 0x00000700;
    BANKCON1 = 0x00000700;
    BANKCON2 = 0x00000700;
    BANKCON3 = 0x00000700;
    BANKCON4 = 0x00000700;
    BANKCON5 = 0x00000700;
    BANKCON6 = (0x3<<15)|(0x01<<2)|0x01;
    BANKCON7 = (0x3<<15)|(0x01<<2)|0x01;
    REFRESH = ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT);
    BANKSIZE = 0x32;
    MRSRB6 = 0x30;
    MRSRB7 = 0x30;
}

 初始化内存就是要配置这十三个寄存器：

 BWSCON:

tq2440的bank用途：其中bank1,2用于ide,bank3没用,bank4 是dm9000, bank5没用, bank6-sdram ,bank7没用。现在要初始化内存所以只设定bank6，其它的bank不管。

DW6=0b10; //bus width for bank 6 is 32bit

WS6=0;    //Disable WAIT,不使用wait信号 (这个东东没有搞明白)

ST6=0;    //Not using UB/LB(Upper Byte/Lower Byte) (这个东东没有搞明白，应该是只有SRAM才有的东东)

BANKCON0-BANKCON5

BANKCON6-BANKCON7:

MT=0b11 ;// Sync. DRAM

Trcd = 0b01;//RAS to CAS delay 3clock （这个东东没有搞明白)

SCAN = 0b01;//Column address numbe ;从A0-A8共9根

2.3 main.c

#define GPBCON (*(volatile unsigned int *) 0x56000010)
#define GPBDAT (*(volatile unsigned int *) 0x56000014)

static inline void delay (unsigned long loops)
{
    __asm__ volatile ("1:\n"
            "subs %0, %1, #1\n"
            "bne 1b":"=r" (loops):"0" (loops));
}

void main(void)
{
    int i = 1;
    int *p = (int*) 0x30000000;
    GPBCON = 0x15400;
    /*测试sdram,向0x30000000写入一个数，并读取，如果没有改变，则说明sdram初始化成功*/
    *p = 0x12345678;
    if(0x12345678 == *p)
    {
/*如果成功，则灯全亮*/
        GPBDAT = 0;
        delay(400000);
    }
    while(1)
    {
        GPBDAT = 0x7FF&(~i<<5);
        i *= 2;
        if(16==i)
            i = 1;
    }
    return ;
}

注：

内存初始化部分是通过天嵌的u-boot中lowlevel_init.S改过来的，有些东东还不是很清楚，完全自己写还有难度。