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5、Internet中断体系--s3c2440

分类： LINUX

2011-03-15 11:32:05

一、S3C2440中断控制要点

    S3C2440A 中的中断控制器可以从60 个中断源接收中断请求。这些中断源由内部外设提供，例如DMA 控制器、UART、IIC 等。在这些中断源中，UARTn、AC97 和外部中断EINTn 对于中断控制器来说是或逻辑。当接收来自内部外设和外部中断请求引脚的多个中断请求时，在仲裁过程后中断控制器请求ARM920T 的FIR 或IRQ 中断。

                                 图1 中断流程图

    如果在ARM920T 的CPU 中的程序状态寄存器的F 位置1，CPU 不能接收来自中断控制器的FIR，如果程序状态寄存器的L 位被置1，则CPU 不能接收来自中断控制器的IRQ。所以，通过清0 程序状态寄存器中的F 位和L 位且清0INTMSK 寄存器中的相应位，中断控制器可以接收中断。

   
 

二、寄存器设置

SRCPND 0X4A000000 R/W Indicate the interrupt request status.

0 = The interrupt has not been requested.

1 = The interrupt source has asserted。

 
 
 
 
三、中断程序源代码
     start.S
  1. /*
  3. *************************************************************************
  5. *
  7. * lcl bootloader
  9. *
  11. *************************************************************************
  13. */
  15. .globl _start
  17. _start: b start_code
  21. HandleUndef:
  23. b HandleUndef @ 0x04: 指未定义指令终止模式的向量地址
  27. HandleSWI:
  29. b HandleSWI @ 0x08 指管理模式，通过SWI指令进入
  33. HandlePerfetchAbort:
  35. b HandlePerfetchAbort @ 0x0c: 指令预取终止导致的异常的向量地址
  39. HandleDataAbort:
  41. b HandleDataAbort @ 0x10: 数据访问终止导致的异常的向量地址
  45. HandleNotUsed:
  47. b HandleNotUsed @ 0x14: 保留
  51. b HandleIRQ @ 0x18: 中断模式的向量地址
  55. HandleFIQ:
  57. b HandleFIQ @ 0x1c: 快中断模式的向量地址
  61. start_code:
  65. bl clock_init
  67. bl cpu_init_crit
  71. msr cpsr_c,#0xd2 @进入中断模式
  73. ldr sp,=3072 @设置中断模式堆栈指针
  77. msr cpsr_c,#0xdf @进入系统模式
  79. msr cpsr_c,#0x5f @开IRQ中断
  81. /*
  83. *run in sdram
  85. */
  89. ldr sp, =4096
  91. ldr lr, =halt_loop @返回地址
  93. ldr pc, = Main
  97. halt_loop:
  99. b halt_loop
  103. HandleIRQ:
  105. sub lr,lr,#4
  107. stmdb sp!,{r0-r12,lr} @保存使用到的寄存器至中断堆栈区
  109. ldr lr,=int_return @设置ISR的返回地址
  111. ldr pc,=EINT_Handle @调用中断服务函数
  113. int_return:
  115. ldmia sp!,{r0-r12,pc}^ @中断返回，恢复寄存器值，^表示将spsr的值复制到cpsr
  119. clock_init:
  121. #define pWTCON 0x53000000
  123. #define CLKDIVN 0x4C000014 /* clock divisor register */
  125. #define CLK_CTL_BASE 0x4C000000 /* clock base address */
  129. #define MDIV_405 0x7f << 12 /* MDIV 0x7f*/
  131. #define PSDIV_405 0x21 /* PDIV SDIV 0x2 0x1 */
  135. /* turn off the watchdog */
  139. ldr r0, =pWTCON
  141. mov r1, #0x0
  143. str r1, [r0]
  147. /* FCLK:HCLK:PCLK = 1:4:8 */
  149. ldr r0, =CLKDIVN
  151. mov r1, #5 //1:4:8
  153. str r1, [r0]
  157. mrc p15, 0, r1, c1, c0, 0 //切换到实时总线HCLK
  159. orr r1, r1, #0xc0000000
  161. mcr p15, 0, r1, c1, c0, 0
  167. mov r1, #CLK_CTL_BASE
  169. mov r2, #MDIV_405
  171. add r2, r2, #PSDIV_405
  173. str r2, [r1, #0x04] /* MPLLCON address Mpll=405MHZ */
  175. mov pc, lr
  177. /*
  179. *MMU and SDRAM initialize
  181. */
  185. cpu_init_crit:
  187. /*
  189. * flush v4 I/D caches
  191. */
  193. mov r0, #0
  195. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  197. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  201. /*
  203. * disable MMU stuff and caches
  205. */
  207. mrc p15, 0, r0, c1, c0, 0
  209. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  211. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  213. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  215. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  217. mcr p15, 0, r0, c1, c0, 0
  221. /*
  223. * before relocating, we have to setup RAM timing
  225. * because memory timing is board-dependend, you will
  227. * find a lowlevel_init.S in your board directory.
  229. */
  231. mov ip, lr
  235. bl memsetup /* memory control configuration */
  239. mov lr, ip
  241. mov pc, lr
  245. memsetup:
  247. /* memory control configuration */
  249. /* make r0 relative the current location so that it */
  251. /* reads SMRDATA out of FLASH rather than memory ! */
  255. #define MEM_CTL_BASE 0x48000000
  259. mov r1,#MEM_CTL_BASE
  261. adr r2,mem_cfg_val
  263. add r3,r1,#52
  265. 1:
  267. ldr r4, [r2], #4
  269. str r4, [r1], #4
  271. cmp r1, r3
  273. bne 1b
  275. mov pc,lr
  279. .align 4
  281. /* the literal pools origin */
  283. mem_cfg_val:
  285. .long 0x22011110
  287. .long 0x00000700
  289. .long 0x00000700
  291. .long 0x00000700
  293. .long 0x00000700
  295. .long 0x00000700
  297. .long 0x00000700 @BANK5
  299. .long 0x00018005
  301. .long 0x00018005
  303. .long 0x00ac03f4 @REFRESH // 12MHZ 0x00ac07a3
  305. .long 0x000000B1
  307. .long 0x00000030
  309. .long 0x00000030
    def.h
  1. #ifndef __DEF_H__
  2. #define __DEF_H__

  4. #define U32 unsigned int
  5. #define U16 unsigned short
  6. #define S32 int
  7. #define S16 short int
  8. #define U8 unsigned char
  9. #define    S8 char

  11. #define __REGb(x)    (*(volatile unsigned char *)(x))
  12. #define __REGw(x)    (*(volatile unsigned short *)(x))
  13. #define __REGi(x)    (*(volatile unsigned int *)(x))

  15. #endif /*__DEF_H__*/
    s3c2440_addr.h
  1. #ifndef _s3c2440_addr_h_
  2. #define _s3c2440_addr_h_

  4. #include "def.h"

  6. /***********uart address*********************/

  8. #define UART_CTL_BASE        0x50000000
  9. #define UART0_CTL_BASE        UART_CTL_BASE
  10. #define UART1_CTL_BASE        UART_CTL_BASE + 0x4000
  11. #define UART2_CTL_BASE        UART_CTL_BASE + 0x8000


  14. #define ULCON0            __REGi(UART0_CTL_BASE + 0x00)    /* R/W, UART line control register */
  15. #define UCON0            __REGi(UART0_CTL_BASE + 0x04)    /* R/W, UART control register */
  16. #define UFCON0            __REGi(UART0_CTL_BASE + 0x08)    /* R/W, UART FIFO control register */
  17. #define UMCON0            __REGi(UART0_CTL_BASE + 0x0C)    /* R/W, UART modem control register */
  18. #define UTRSTAT0        __REGi(UART0_CTL_BASE + 0x10)    /* R , UART Tx/Rx status register */
  19. #define UERSTAT0        __REGi(UART0_CTL_BASE + 0x14)    /* R , UART Rx error status register */
  20. #define UFSTAT0            __REGi(UART0_CTL_BASE + 0x18)    /* R , UART FIFO status register */
  21. #define UMSTAT0            __REGi(UART0_CTL_BASE + 0x1C)    /* R , UART Modem status register */
  22. #define UTXH0            __REGb(UART0_CTL_BASE + 0x20)    /* W 8bit , UART transmit(little-end) buffer */
  23. #define URXH0            __REGb(UART0_CTL_BASE + 0x24)    /* R 8bit , UART receive(little-end) buffer */
  24. #define UBRDIV0            __REGi(UART0_CTL_BASE + 0x28)    /* R/W, Baud rate divisor register */

  26. /* ... */
  27. #define UTRSTAT_TX_EMPTY    (1 << 2)
  28. #define UTRSTAT_RX_READY    (1 << 0)
  29. #define UART_ERR_MASK        0xF

  31. #define UART_BAUD_RATE        115200
  32. #define UART_PCLK_405_148 50625000
  33. #define UART_PCLK UART_PCLK_405_148
  34. #define UART_BRD ((UART_PCLK / (UART_BAUD_RATE * 16)) - 1)
  35.   

  37. /***********GPB GPG GPH GPIO address*********************/

  39. #define GPBCON (*(volatile unsigned long *) 0x56000010)
  40. #define GPBDAT (*(volatile unsigned long *) 0x56000014)
  41. #define GPBUP (*(volatile unsigned long *) 0x56000018)

  43. #define GPGCON (*(volatile unsigned long *) 0x56000060)
  44. #define GPGDAT (*(volatile unsigned long *) 0x56000064)
  45. #define GPGUP (*(volatile unsigned long *) 0x56000068)

  47. #define GPHCON         __REGi(0x56000070)             //R/W      Configures the pins of port H                             0x0

  49. #define GPHDAT          __REGi(0x56000074)             //R/W      The data register for port H                             Undef.

  51. #define GPHUP     __REGi(0x56000078)             //R/W      pull-up disable register for port H


  54. /* .. */    
  55. #define GPX_up              0x00000000 // up

  57. #define GPX_mask(pin) (~(3<<((pin)*2)))
  58. #define BIT_mask(pin) (~(1<<(pin)))

  60.     
  61.     
  62. #define GPH_tx0         (2<<(2*2))                     //10 = TXD[0]

  64. #define GPH_rx0         (2<<(3*2))                     //10 = RXD[0]


  67. #define GPB5_out          (1<<(5*2))
  68. #define GPB6_out          (1<<(6*2))
  69. #define GPB7_out          (1<<(7*2))
  70. #define GPB8_out          (1<<(8*2))

  72. #define GPG0_in          (0<<(0*2))
  73. #define GPG3_in          (0<<(3*2))
  74. #define GPG5_in          (0<<(5*2))
  75. #define GPG6_in          (0<<(6*2))

  77. #define GPG0_eint8      (2<<(0*2))
  78. #define GPG3_eint11      (2<<(3*2))
  79. #define GPG5_eint13      (2<<(5*2))
  80. #define GPG6_eint14      (2<<(6*2))

  82. /*****************timer register*****************/

  84. #define TCFG0 (*(volatile unsigned long *) 0x51000000)
  85. #define TCFG1 (*(volatile unsigned long *) 0x51000004)
  86. #define TCON (*(volatile unsigned long *) 0x51000008)
  87. #define TCNTB0 (*(volatile unsigned long *) 0x5100000C)
  88. #define TCMPB0 (*(volatile unsigned long *) 0x51000010)
  89. #define TCNTO0 (*(volatile unsigned long *) 0x51000014)

  91. /* .. */
  92. #define GPB0_pwm         (2<<(0*2))

  94. /*****************interrupt register*****************/
  95. #define INT_CTL_BASE        0x4A000000

  97. #define SRCPND            __REGi(INT_CTL_BASE + 0x00)
  98. #define INTMOD            __REGi(INT_CTL_BASE + 0x04)
  99. #define INTMSK            __REGi(INT_CTL_BASE + 0x08)
  100. #define PRIORITY        __REGi(INT_CTL_BASE + 0x0c)
  101. #define INTPND            __REGi(INT_CTL_BASE + 0x10)
  102. #define INTOFFSET        __REGi(INT_CTL_BASE + 0x14)
  103. #define SUBSRCPND        __REGi(INT_CTL_BASE + 0x18)
  104. #define INTSUBMSK        __REGi(INT_CTL_BASE + 0x1c)

  106. #define EINTMASK __REGi(0x560000A4) /*External interrupt mask register*/
  107. #define EINTPEND __REGi(0x560000A8) /*External interrupt pending register*/

  109. /* ... */
  110. #define INT_ADCTC        (1 << 31)    /* ADC EOC interrupt */
  111. #define INT_RTC            (1 << 30)    /* RTC alarm interrupt */
  112. #define INT_SPI1        (1 << 29)    /* UART1 transmit interrupt */
  113. #define INT_UART0        (1 << 28)    /* UART0 transmit interrupt */
  114. #define INT_IIC            (1 << 27)    /* IIC interrupt */
  115. #define INT_USBH        (1 << 26)    /* USB host interrupt */
  116. #define INT_USBD        (1 << 25)    /* USB device interrupt */
  117. #define INT_RESERVED24    (1 << 24)
  118. #define INT_UART1        (1 << 23)    /* UART1 receive interrupt */
  119. #define INT_SPI0        (1 << 22)    /* SPI interrupt */
  120. #define INT_MMC            (1 << 21)    /* MMC interrupt */
  121. #define INT_DMA3        (1 << 20)    /* DMA channel 3 interrupt */
  122. #define INT_DMA2        (1 << 19)    /* DMA channel 2 interrupt */
  123. #define INT_DMA1        (1 << 18)    /* DMA channel 1 interrupt */
  124. #define INT_DMA0        (1 << 17)    /* DMA channel 0 interrupt */
  125. #define INT_LCD            (1 << 16)    /* reserved for future use */
  126. #define INT_UART2        (1 << 15)    /* UART 2 interrupt */
  127. #define INT_TIMER4        (1 << 14)    /* Timer 4 interrupt */
  128. #define INT_TIMER3        (1 << 13)    /* Timer 3 interrupt */
  129. #define INT_TIMER2        (1 << 12)    /* Timer 2 interrupt */
  130. #define INT_TIMER1        (1 << 11)    /* Timer 1 interrupt */
  131. #define INT_TIMER0        (1 << 10)    /* Timer 0 interrupt */
  132. #define INT_WDT            (1 << 9)    /* Watch-Dog timer interrupt */
  133. #define INT_TICK        (1 << 8)    /* RTC time tick interrupt */
  134. #define INT_BAT_FLT        (1 << 7)
  135. #define INT_RESERVED6        (1 << 6)    /* Reserved for future use */
  136. #define INT_EINT8_23        (1 << 5)    /* External interrupt 8 ~ 23 */
  137. #define INT_EINT4_7        (1 << 4)    /* External interrupt 4 ~ 7 */
  138. #define INT_EINT3        (1 << 3)    /* External interrupt 3 */
  139. #define INT_EINT2        (1 << 2)    /* External interrupt 2 */
  140. #define INT_EINT1        (1 << 1)    /* External interrupt 1 */
  141. #define INT_EINT0        (1 << 0)    /* External interrupt 0 */

  143. #define INT_ADC            (1 << 10)
  144. #define INT_TC            (1 << 9)
  145. #define INT_ERR2        (1 << 8)
  146. #define INT_TXD2        (1 << 7)
  147. #define INT_RXD2        (1 << 6)
  148. #define INT_ERR1        (1 << 5)
  149. #define INT_TXD1        (1 << 4)
  150. #define INT_RXD1        (1 << 3)
  151. #define INT_ERR0        (1 << 2)
  152. #define INT_TXD0        (1 << 1)
  153. #define INT_RXD0        (1 << 0)

  155. #endif
    usrt0_init.h
  1. #ifndef __UART0_INIT_H__
  2. #define __UART0_INIT_H__

  4. void uart0_init();
  5. void Uart_SendString(char *pt);

  7. #endif
uart0_init.c
  1. /*
  2.   * uart0 lib
  3.   */
  4. #include "s3c2440_addr.h"

  6. void uart0_init()
  7. {
  8.     GPHCON &= (GPX_mask(2) & GPX_mask(3));
  9.     GPHCON |= GPH_tx0 | GPH_rx0;
  10.     GPHUP |= 0x0c;

  12.     ULCON0 = (0<< 3) | (0<< 2) | (3<< 0); // 8N1 ;normal mode , no parity , 1stop bit,8bit

  14.    UCON0 = (0<<10) | (1<< 9) | (1<< 6) | (1<< 2) | (1<< 0); // Select PCLK for the UART baud rate,polling mode, [9][6]:1 1

  16.    UFCON0 = 0x00;                          // disable FIFO

  18.    UMCON0 = 0x00;                          // disable AFC


  21.     UBRDIV0 = UART_BRD;                      // baud rate divisior 115200



  25. }

  27. static inline void putc(char data)
  28. {
  29.     while (!(UTRSTAT0 & 0x4)) ;                //Wait until THR is empty.

  31.     UTXH0 = data;
  32. }

  34. static inline unsigned char getc(void)
  35. {
  36.     while (!(UTRSTAT0 & (1))) ;                //Wait until THx is empty.

  38.     return URXH0;
  39. }

  41. void Uart_SendString(char *pt)
  42. {
  43.     while (*pt)
  44.         putc(*pt++);
  45. }
    mem.lds
  1. /*
  2.  *lcl bootloader mem.lds
  3.  */

  5. OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  6. OUTPUT_ARCH(arm)
  7. ENTRY(_start)

  9. SECTIONS {
  10.   . = 0x00000000;

  12.   . = ALIGN(4);
  13.   .init : AT(0) {start.o}

  15.   . = 0x00000800;
  16.   .text : AT(2048) { *(.text) }
  17.     
  18.   .rodata ALIGN(4) : AT((LOADADDR(.text)+SIZEOF(.text)+3)&~(0x03)) { *(.rodata*) }

  20.   .data ALIGN(4) : AT((LOADADDR(.rodata)+SIZEOF(.rodata)+3)&~(0x03)) { *(.data) }
  21.   
  22.   . = ALIGN(4);
  23.   __bss_start = .;
  24.   .bss :{ *(.bss) *(COMMON)}
  25.   __bss_end = .;
  26. }
    Makefile
  1. objs := start.o main.o uart0_init.o interrupt.o

  3. sdram.bin : $(objs)
  4.     arm-linux-ld -Tmem.lds    -o sdram_elf $^
  5.     arm-linux-objcopy -O binary -S sdram_elf $@
  6.     arm-linux-objdump -D -m arm sdram_elf > sdram.dis
  7.     arm-linux-objdump -dx sdram_elf > mem_bin.map
  8.     rm -f sdram.dis sdram_elf *.o

  10. %.o:%.c
  11.     arm-linux-gcc -Wall -c -O2 -o $@ $<

  13. %.o:%.S
  14.     arm-linux-gcc -Wall -c -O2 -o $@ $<

  16. clean:
  17.     rm -f sdram.bin mem_bin.map
    main.c
  1. /*
  2. GPBCON 0x56000010 Port B control
  3. GPBDAT 0x56000014 Port B data
  4. GPBUP 0x56000018 Pull-up control B

  6. LED1 GPB5 LED2 GPB6 LED3 GPB7 LED4 GPB8

  8. */

  10. #include "uart0_init.h"
  11. #include "s3c2440_addr.h"
  12. #include "interrupt.h"

  14. void leds_init()
  15. {
  16.     /*GPBCON &= (GPX_mask(5) & GPX_mask(6) & GPX_mask(7) & GPX_mask(8));
  17.     GPBCON |= (GPB5_out | GPB6_out | GPB7_out | GPB8_out);
  18.     GPBUP = GPX_up;
  19.     GPBDAT |=( 0xf << 5 );*/
  20.     GPBCON = (GPB5_out | GPB6_out | GPB7_out | GPB8_out);
  21.     GPBUP     = GPX_up;
  22. }
  23. void buttons_eint_init()
  24. {
  25.     GPGCON &= (GPX_mask(0) & GPX_mask(3) & GPX_mask(5) & GPX_mask(6));
  26.     GPGCON |= (GPG0_eint8 | GPG3_eint11 | GPG5_eint13 | GPG6_eint14);
  27. }

  29. int Main()
  30. {
  31.     unsigned long dwDat;
  32.     leds_init();
  33.     buttons_eint_init();
  34.     uart0_init();
  35.     irq_init();
  36.         
  37.     GPBDAT |=( 0xf << 5 );
  38.     
  39.     Uart_SendString("\r wait interrupt. \r\n");    

  41.     while (1)
  42.     {
  43.     GPBDAT |=( 0xf << 5 );
  44.     }

  46.     return 0;
  47. }
 
以下为能直接运行的二进制文件，下载到Nand Flash 的 Black0 直接以Nand Flash运行。
 
 
 
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