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3、NAND Flash控制器--s3c2440

分类： LINUX

2011-03-13 23:17:20

一、NAND Flash关键硬件知识
    采用k9f2g08x0a NAND　Flash芯片 ：（其芯片手册可在网上下载）
Organization
    - Memory Cell Array : (256M 8M) x 8bit
    - Data Register : (2K 64) x 8bit
Automatic Program and Erase
    - Page Program : (2K 64)Byte
    - Block Erase : (128K 4K)Byte
Page Read Operation
   - Page Size : (2K 64)Byte

                               图1 NAND Flash 结构组织

                            图2  NAND Flash命令表 

 

二、NAND Flash 控制寄存器
    NAND FLASH 还是 NOR Flash 配置，硬件电路已设计好，仅供加深理解。
  
                    图3  PIN CONFIGURATION
                           

NFCONF 0x4E000000 R/W  NAND flash configuration register  0x0000100X

 推荐值TACLS=0  TWRPH0=6  TWRPH1=2 buswitdth 8bit (TACLS+TWRPH0+TWRPH1>=50ns)

NFCONT 0x4E000004 R/W NAND flash control register 0x0384

推荐值 (1<<4) | (1<<1) | (1<<0) 

 

 

 

 

 

NFCMMD 0x4E000008 R/W NAND flash command set register 0x00

NFCMMD [7:0]     NAND flash memory command value      0x00

NFADDR 0x4E00000C R/W NAND flash address set register 0x0000XX00

NFADDR [7:0]      NAND flash memory address value       0x00

NFDATA 0x4E000010 R/W NAND flash data register 0xXXXX

可8bit 16bit 32bit访问 如图4

NFDATA [31:0]  NAND flash read/program data value for I/O    0xXXXX

                  Note: Refer to data register configuration in Page 6-5.

 

                                                     图4

NFSTAT 0x4E000020 R/W NAND flash operation status register 0xXX00

三、硬件电路图

   

                图4 NAND Flash管脚连接图

四、NAND Flash 读操作

    K9F2G08U0A的一页为（2K＋64）字节（加号前面的2K表示的是main区容量，加号后面的64表示的是spare区容量），它的一块为64页，而整个设备包括了2048个块。这样算下来一共有2112M位容量，如果只算main区容量则有256M字节（即256*8位）。要实现用8个IO口来要访问这么大的容量，K9F2G08U0A规定了用5个周期来实现。第一个周期访问的地址为A0~A7；第二个周期访问的地址为A8~A11，它作用在IO0~IO3上，而此时IO4~IO7必须为低电平；第三个周期访问的地址为A12~A19；第四个周期访问的地址为A20~A27；第五个周期访问的地址为A28，它作用在IO0上，而此时IO1~IO7必须为低电平。前两个周期传输的是列地址，后三个周期传输的是行地址。通过分析可知，列地址是用于寻址页内空间，行地址用于寻址页，如果要直接访问块，则需要从地址A18开始。

                           图4 读操作时序图

五、源代码

   start.S  //引导程序

 

  1. /*
  3. *************************************************************************
  5. *
  7. * lcl bootloader
  9. *
  11. *************************************************************************
  13. */
  15. .globl _start
  17. _start: b start_code
  19. start_code:
  21. /*
  23. * set the cpu to SVC32 mode
  25. */
  27. mrs r0, cpsr
  29. bic r0, r0, #0x1f
  31. orr r0, r0, #0xd3
  33. msr cpsr, r0
  37. #define pWTCON 0x53000000
  39. #define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
  41. #define INTSUBMSK 0x4A00001C
  43. #define CLKDIVN 0x4C000014 /* clock divisor register */
  45. #define CLK_CTL_BASE 0x4C000000 /* clock base address */
  49. #define MDIV_405 0x7f << 12 /* MDIV 0x7f*/
  51. #define PSDIV_405 0x21 /* PDIV SDIV 0x2 0x1 */
  55. /* turn off the watchdog */
  59. ldr r0, =pWTCON
  61. mov r1, #0x0
  63. str r1, [r0]
  67. /*
  69. * mask all IRQs by setting all bits in the INTMR - default
  71. */
  75. ldr r1, =0x7fff
  77. ldr r0, =INTSUBMSK
  79. str r1, [r0]
  83. /* FCLK:HCLK:PCLK = 1:4:8 */
  85. ldr r0, =CLKDIVN
  87. mov r1, #5 //1:4:8
  89. str r1, [r0]
  93. mrc p15, 0, r1, c1, c0, 0
  95. orr r1, r1, #0xc0000000
  97. mcr p15, 0, r1, c1, c0, 0
  101. mov r1, #CLK_CTL_BASE
  103. mov r2, #MDIV_405
  105. add r2, r2, #PSDIV_405
  107. str r2, [r1, #0x04] /* MPLLCON address Mpll=405MHZ */
  111. nop
  113. nop
  115. nop
  117. nop
  119. nop
  121. nop
  123. nop
  125. nop
  127. nop
  129. /*
  131. *MMU and SDRAM initialize
  133. */
  137. bl cpu_init_crit
  141. /*
  143. *call c function . sp is 0x34000000
  145. */
  147. mov fp, #0 // no previous frame, so fp=0
  149. ldr sp, =0x34000000
  151. bl NandInit
  153. bl ReadImageFromNand
  157. /*
  159. *run in sdram
  161. */
  165. ldr lr, =halt_loop @设置返回地址
  167. ldr pc, =Main //0x30000834
  169. halt_loop:
  171. b halt_loop
  175. .globl ReadPage512
  177. ReadPage512: //读512字节
  179. stmfd sp!, {r2-r7}
  181. mov r2, #0x200
  183. 1:
  185. ldr r4, [r1] //取出32bit，按8bit字访问
  187. ldr r5, [r1] //取出32bit
  189. ldr r6, [r1] //取出32bit
  191. ldr r7, [r1] //取出32bit
  193. stmia r0!, {r4-r7} //存 64bit 到buffer中
  195. ldr r4, [r1]
  197. ldr r5, [r1]
  199. ldr r6, [r1]
  201. ldr r7, [r1]
  203. stmia r0!, {r4-r7} //存 64bit 到buffer中
  205. ldr r4, [r1]
  207. ldr r5, [r1]
  209. ldr r6, [r1]
  211. ldr r7, [r1]
  213. stmia r0!, {r4-r7} //存 64bit 到buffer中
  215. ldr r4, [r1]
  217. ldr r5, [r1]
  219. ldr r6, [r1]
  221. ldr r7, [r1]
  223. stmia r0!, {r4-r7} //存 64bit 到buffer中
  225. subs r2, r2, #64 //减去已读出的64byte
  227. bne 1b; //循环读出直到512byte
  229. ldmfd sp!, {r2-r7}
  231. mov pc,lr //返回
  235. cpu_init_crit:
  237. /*
  239. * flush v4 I/D caches
  241. */
  243. mov r0, #0
  245. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  247. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  251. /*
  253. * disable MMU stuff and caches
  255. */
  257. mrc p15, 0, r0, c1, c0, 0
  259. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  261. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  263. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  265. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  267. mcr p15, 0, r0, c1, c0, 0
  271. /*
  273. * before relocating, we have to setup RAM timing
  275. * because memory timing is board-dependend, you will
  277. * find a lowlevel_init.S in your board directory.
  279. */
  281. mov ip, lr
  285. bl memsetup /* memory control configuration */
  289. mov lr, ip
  291. mov pc, lr
  295. memsetup:
  297. /* memory control configuration */
  299. /* make r0 relative the current location so that it */
  301. /* reads SMRDATA out of FLASH rather than memory ! */
  305. #define MEM_CTL_BASE 0x48000000
  309. mov r1,#MEM_CTL_BASE
  311. adr r2,mem_cfg_val
  313. add r3,r1,#52
  315. 1:
  317. ldr r4, [r2], #4
  319. str r4, [r1], #4
  321. cmp r1, r3
  323. bne 1b
  325. mov pc,lr
  329. .align 4
  331. /* the literal pools origin */
  333. mem_cfg_val:
  335. .long 0x22011110
  337. .long 0x00000700
  339. .long 0x00000700
  341. .long 0x00000700
  343. .long 0x00000700
  345. .long 0x00000700
  347. .long 0x00000700 @BANK5
  349. .long 0x00018005
  351. .long 0x00018005
  353. .long 0x00ac03f4 @REFRESH // 12MHZ 0x00ac07a3
  355. .long 0x000000B1
  357. .long 0x00000030
  359. .long 0x00000030

  def.h

 

  1. #ifndef __DEF_H__
  2. #define __DEF_H__

  4. #define U32 unsigned int
  5. #define U16 unsigned short
  6. #define S32 int
  7. #define S16 short int
  8. #define U8 unsigned char
  9. #define    S8 char

  11. #endif /*__DEF_H__*/

nand.h

 

  1. #ifndef __NAND_H
  2. #define __NAND_H

  4. void NandInit(void);
  5. int NandIsGoodBlock(U32 addr);
  6. int NandReadOneSector(U8 * buffer, U32 addr);

  8. void Uart_SendString(char *);

  10. #define PAGE_UNKNOWN 0
  11. #define PAGE512 1
  12. #define PAGE2048 2 //本芯片为2K一页

  14. #define BYTE_SECTOR_SHIFT (g_page_type == PAGE512 ? 9 : 11) //2K a page=11bit

  16. #define SECTOR_BLOCK_SHIFT (g_page_type == PAGE512 ? 5 : 6) //64 pages=6bit

  18. #define SECTOR_SIZE (1 << BYTE_SECTOR_SHIFT) //2K

  20. #define BLOCK_SIZE (SECTOR_SIZE << SECTOR_BLOCK_SHIFT) //128K

  22. extern int g_page_type;

  24. #endif /*__NAND_H*/

nand.c

 

  1. #include "def.h"
  2. #include "nand.h"

  4. /***********nand flash address*********************/
  5. #define __REGb(x)    (*(volatile unsigned char *)(x))
  6. #define __REGw(x)    (*(volatile unsigned short *)(x))
  7. #define __REGi(x)    (*(volatile unsigned int *)(x))
  8. #define NF_BASE        0x4e000000

  10. #define NFCONF        __REGi(NF_BASE + 0x0)
  11. #define NFCONT        __REGi(NF_BASE + 0x4)
  12. #define NFCMD        __REGb(NF_BASE + 0x8)
  13. #define NFADDR        __REGb(NF_BASE + 0xc)
  14. #define NFDATA        __REGb(NF_BASE + 0x10)
  15. #define NFSTAT        __REGb(NF_BASE + 0x20)
  16. /***********nand flash address end*********************/

  18. #define NF_MECC_UnLock() {NFCONT&=~(1<<5);}
  19. #define NF_MECC_Lock() {NFCONT|=(1<<5);}

  21. #define NF_CMD(cmd)            {NFCMD=cmd;}
  22. #define NF_ADDR(addr)        {NFADDR=addr;}
  23. #define NF_nFCE_L()            {NFCONT&=~(1<<1);}
  24. #define NF_nFCE_H()            {NFCONT|=(1<<1);}
  25. #define NF_RSTECC()            {NFCONT|=(1<<4);}
  26. #define NF_RDDATA8()         (NFDATA)

  28. #define NF_WAITRB()         {while(!(NFSTAT&(1<<1)));}
  29.                              //wait tWB and check F_RNB pin.

  31. // RnB Signal

  33. #define NF_CLEAR_RB()     {NFSTAT |= (1<<2);}    // Have write '1' to clear this bit.

  35. #define NF_DETECT_RB()     {while(!(NFSTAT&(1<<2)));}

  37. #define TACLS        0    // 1-clk(0ns)

  39. #define TWRPH0        6    // 3-clk(25ns)

  41. #define TWRPH1        2    // 1-clk(10ns) //TACLS+TWRPH0+TWRPH1>=50ns



  45. #define ECC_VERIFY    0

  47. int g_page_type = PAGE_UNKNOWN;

  49. extern void ReadPage512(U8* buf, volatile unsigned char *nf_data_ptr);

  51. static inline void NandReset(void)
  52. {
  53.     NF_nFCE_L();
  54.     NF_CLEAR_RB();
  55.     NF_CMD(0xFF);        //reset command

  57.     NF_DETECT_RB();
  58.     NF_nFCE_H();

  60. }

  62. static inline void delay(void)
  63. {
  64. #if 0
  65.     volatile int i;
  66.     for (i = 0; i < 1000; i++);
  67. #endif
  68. }

  70. static inline U32 NandCheckId(void)
  71. {
  72.     U8 Mid, Did, DontCare, id4th;

  74.     NF_nFCE_L();

  76.     NF_CMD(0x90);
  77.     NF_ADDR(0x0);

  79.     delay();

  81.     Mid = NF_RDDATA8();
  82.     Did = NF_RDDATA8();
  83.     DontCare = NF_RDDATA8();
  84.     id4th = NF_RDDATA8();

  86.     NF_nFCE_H();

  88.     switch(Did) { /*选择各种支持的芯片类型*/
  89.     case 0x76:
  90.         g_page_type = PAGE512;/* Samsung K91208 * *Hynix HY27US08121A*/
  91.         break;
  92.     case 0xF1:    /* Samsung K9F1G08U0B */
  93.     case 0xD3: /* Samsung K9K8G08 */
  94.     case 0xDA: /* Samsung K9F2G08U0B */
  95.     case 0xDC:
  96.         g_page_type = PAGE2048;
  97.         break;
  98.     default:
  99.         ;
  100.     }


  103.     return (U32) ((Mid << 24) | (Did << 16) | (DontCare << 8) | id4th);
  104. }

  106. void NandInit(void)
  107. {
  108.     NFCONF = (TACLS << 12) | (TWRPH0 << 8) | (TWRPH1 << 4) | (0 << 0);
  109.     NFCONT =
  110.      (0 << 13) | (0 << 12) | (0 << 10) | (0 << 9) | (0 << 8) | (0 << 6) |
  111.      (0 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
  112.     NFSTAT = 0;
  113.     NandReset();
  114.     NandCheckId();
  115.     return ;
  116. }

  118. static inline int NandIsGoodBlockP512(U32 addr)
  119. {
  120.     U32 sector = addr >> 9;
  121.     U8 bad_value;

  123.     NandReset();
  124.     NF_nFCE_L();
  125.     NF_CLEAR_RB();
  126.     NF_CMD(0x50);
  127.     NF_ADDR(5);
  128.     NF_ADDR(sector & 0xff);
  129.     NF_ADDR((sector >> 8) & 0xff);
  130.     NF_ADDR((sector >> 16) & 0xff);

  132.     delay();
  133.     NF_DETECT_RB();

  135.     bad_value = NF_RDDATA8();

  137.     NF_nFCE_H();

  139.     if (bad_value == 0xFF) {
  140.         return 1;
  141.     }

  143.     return 0;
  144. }

  146. static inline int NandIsGoodBlockP2048(U32 addr)
  147. {
  148.     U32 sector = addr >> 11;
  149.     U8 bad_value;

  151.     NandReset();
  152.     NF_nFCE_L();
  153.     NF_CLEAR_RB();
  154.     NF_CMD(0x0);
  155.     NF_ADDR(2048 & 0xFF);
  156.     NF_ADDR((2048 >>8) & 0xff);
  157.     NF_ADDR(sector & 0xff);
  158.     NF_ADDR((sector >> 8) & 0xff);
  159.     NF_ADDR((sector >> 16) & 0xff);
  160.     NF_CMD(0x30);
  161.     delay();
  162.     NF_DETECT_RB();

  164.     bad_value = NF_RDDATA8();

  166.     NF_nFCE_H();

  168.     if (bad_value == 0xFF) {
  169.         return 1;
  170.     }

  172.     return 0;
  173. }

  175. int NandIsGoodBlock(U32 addr)
  176. {
  177.     int ret;
  178.     
  179.     switch(g_page_type) {
  180.     case PAGE512:
  181.         {
  182.             unsigned int i;
  183.             // for ugly method of Chen Yongqiang

  185.             for (i = 0; i < 128 * 1024; i+= 16 * 1024) {
  186.                 ret = NandIsGoodBlockP512(addr / (128 * 1024) * (128 * 1024) + i );
  187.                 if (!ret) {
  188.                     break;
  189.                 }
  190.             }
  191.         }
  192.         break;
  193.     case PAGE2048:
  194.         ret = NandIsGoodBlockP2048(addr);
  195.         break;
  196.     default:
  197.         for(;;);
  198.     }
  199.     return ret;
  200. }

  202. static inline int NandReadOneSectorP512(U8 * buffer, U32 addr)
  203. {
  204.     U32 sector;
  205.     sector = addr >> 9;

  207.     NandReset();
  208. #if 0
  209.     NF_RSTECC();
  210.     NF_MECC_UnLock();
  211. #endif
  212.     NF_nFCE_L();

  214.     NF_CLEAR_RB();
  215.     NF_CMD(0x00);

  217.     NF_ADDR(0x00);
  218.     NF_ADDR(sector & 0xff);
  219.     NF_ADDR((sector >> 8) & 0xff);
  220.     NF_ADDR((sector >> 16) & 0xff);

  222.     delay();
  223.     NF_DETECT_RB();

  225.     ReadPage512(buffer, &NFDATA);
  226. #if 0
  227.     NF_MECC_Lock();
  228. #endif
  229.     NF_nFCE_H();

  231.     return 1;
  232. }


  235. static inline int NandReadOneSectorP2048(U8 * buffer, U32 addr)
  236. {
  237.     U32 sector;
  238.     sector = addr >> 11;

  240.     delay();
  241.     NandReset();
  242. #if 0
  243.     NF_RSTECC();
  244.     NF_MECC_UnLock();
  245. #endif
  246.     NF_nFCE_L();

  248.     NF_CLEAR_RB();
  249.     NF_CMD(0x00);

  251.     NF_ADDR(0x00);
  252.     NF_ADDR(0x00);
  253.     NF_ADDR(sector & 0xff);
  254.     NF_ADDR((sector >> 8) & 0xff);
  255.     NF_ADDR((sector >> 16) & 0xff);
  256.     NF_CMD(0x30);

  258.     delay();
  259.     NF_DETECT_RB();

  261.     ReadPage512(buffer + 0 * 512, &NFDATA);
  262.     ReadPage512(buffer + 1 * 512, &NFDATA);
  263.     ReadPage512(buffer + 2 * 512, &NFDATA);
  264.     ReadPage512(buffer + 3 * 512, &NFDATA);

  266. #if 0
  267.     NF_MECC_Lock();
  268. #endif
  269.     NF_nFCE_H();

  271.     return 1;
  272. }


  275. int NandReadOneSector(U8 * buffer, U32 addr)
  276. {
  277.     int ret;
  278.     
  279.     switch(g_page_type) {
  280.     case PAGE512:
  281.         ret = NandReadOneSectorP512(buffer, addr);
  282.         break;
  283.     case PAGE2048:
  284.         ret = NandReadOneSectorP2048(buffer, addr);
  285.         break;
  286.     default:
  287.         for(;;);
  288.     }
  289.     return ret;
  290. }

  292. void ReadImageFromNand(void)
  293. {
  294.     unsigned int Length;
  295.     U8 *RAM;
  296.     unsigned BlockNum;
  297.     unsigned pos;

  299.     Length = 0x100000;/*将拷贝NAND Flash 中1M的内容到SDRAM中*/
  300.     Length = (Length + BLOCK_SIZE - 1) >> (BYTE_SECTOR_SHIFT + SECTOR_BLOCK_SHIFT) << (BYTE_SECTOR_SHIFT + SECTOR_BLOCK_SHIFT); // align to Block Size

  302.               /*长度对齐，这很关键*/
  303.     BlockNum = 0x00000 >> (BYTE_SECTOR_SHIFT + SECTOR_BLOCK_SHIFT);//拷贝的起始地址，地址对齐，这很关键不然会使拷贝的程序无法运行

  305.     RAM = (U8 *)0x30000000; //拷贝至SDRAM的起始处

  307.     for (pos = 0; pos < Length; pos += BLOCK_SIZE) {
  308.         unsigned int i;
  309.         // skip badblock

  311.         for (;;) {
  312.             if (NandIsGoodBlock
  313.              (BlockNum <<
  314.              (BYTE_SECTOR_SHIFT + SECTOR_BLOCK_SHIFT))) {
  315.                 break;
  316.             }
  317.             BlockNum++;    //try next

  319.         }
  320.         for (i = 0; i < BLOCK_SIZE; i += SECTOR_SIZE) {
  321.             int ret =
  322.              NandReadOneSector(RAM,
  323.                      (BlockNum <<
  324.                      (BYTE_SECTOR_SHIFT +
  325.                         SECTOR_BLOCK_SHIFT)) + i);
  326.             RAM += SECTOR_SIZE;
  327.             ret = 0;

  329.         }

  331.         BlockNum++;
  332.     }
  333.     return ;
  334. }

main.c

 

  1. /*
  2. GPBCON 0x56000010 Port B control
  3. GPBDAT 0x56000014 Port B data
  4. GPBUP 0x56000018 Pull-up control B

  6. LED1 GPB5 LED2 GPB6 LED3 GPB7 LED4 GPB8

  8. GPB8 [17:16] 00 = Input 01 = Output
  9.              10 = nXDREQ1 11 = Reserved
  10. GPB7 [15:14] 00 = Input 01 = Output
  11.              10 = nXDACK1 11 = Reserved
  12. GPB6 [13:12] 00 = Input 01 = Output
  13.              10 = nXBREQ 11 = reserved
  14. GPB5 [11:10] 00 = Input 01 = Output
  15.              10 = nXBACK 11 = reserved
  16. #define S3C24X0_GPIO_BASE        0x56000000

  18. GPGCON = 0000 0000 1000 0000 1010 1000 1000 0010=0x80a882

  20. GPG0 Input/output EinT8 – – K1
  21. GPG3 Input/output EinT11 nSS1 –     K2
  22. GPG5 Input/output EinT13 SPIMISO1 – k3
  23. GPG6 Input/output EinT14 SPIMISO1 – k4
  24. GPG7 Input/output EinT15 SPICLK1 – k5
  25. GPG11 Input/output EinT19 TCLK1 – k6
  26. */

  28. #define GPBCON (*(volatile unsigned long *) 0x56000010)
  29. #define GPBDAT (*(volatile unsigned long *) 0x56000014)
  30. #define GPBUP (*(volatile unsigned long *) 0x56000018)

  32. #define GPGCON (*(volatile unsigned long *) 0x56000060)
  33. #define GPGDAT (*(volatile unsigned long *) 0x56000064)
  34. #define GPGUP (*(volatile unsigned long *) 0x56000068)

  36. #define GPX_up 0x00000000

  38. #define GPB5_out (1<<(5*2))
  39. #define GPB6_out (1<<(6*2))
  40. #define GPB7_out (1<<(7*2))
  41. #define GPB8_out (1<<(8*2))

  43. #define GPG0_in ~(3<<(0*2))
  44. #define GPG3_in ~(3<<(3*2))
  45. #define GPG5_in ~(3<<(5*2))
  46. #define GPG6_in ~(3<<(6*2))

  48. static inline void leds_init()
  49. {
  50.     GPBCON = (GPB5_out | GPB6_out | GPB7_out | GPB8_out);
  51.     GPBUP     = GPX_up;
  52. }
  53. static inline void buttons_init()
  54. {
  55.     GPGCON = (GPG0_in & GPG3_in & GPG5_in & GPG6_in);
  56.     GPGUP     = GPX_up;
  57. }

  59. int Main()
  60. {
  61.     unsigned long dwDat;
  62.     leds_init();
  63.     buttons_init();

  65.     while (1)
  66.     {
  67.         dwDat=GPGDAT;
  68.         if(dwDat & (1<<0))
  69.             GPBDAT |=(1<<5);
  70.         else
  71.             GPBDAT &=~(1<<5);    

  73.         if(dwDat & (1<<3))
  74.             GPBDAT |=(1<<6);    
  75.         else
  76.             GPBDAT &=~(1<<6);    

  78.         if(dwDat & (1<<5))
  79.             GPBDAT |=(1<<7);
  80.         else
  81.             GPBDAT &=~(1<<7);    

  83.         if(dwDat & (1<<6))
  84.             GPBDAT |=(1<<8);    
  85.         else
  86.             GPBDAT &=~(1<<8);                
  87.     }

  89.     return 0;
  90. }

sdram.lds  //运行地址与实时分配

 

  1. SECTIONS {
  2.   firtst     0x00000000 : { start.o nand.o}
  3.   second     0x30001000 : AT(4096) { main.o }
  4. }

Makefile

 

  1. objs := start.o nand.o main.o

  3. nand_sdram.bin : $(objs)
  4.     arm-linux-ld -Tsdram.lds -o nand_sdram_elf $^
  5.     arm-linux-objcopy -O binary -S nand_sdram_elf $@
  6.     arm-linux-objdump -D -m arm nand_sdram_elf > nand_sdram.dis

  8. %.o:%.c
  9.     arm-linux-gcc -Wall -c -O2 -o $@ $<

  11. %.o:%.S
  12.     arm-linux-gcc -Wall -c -O2 -o $@ $<

  14. clean:
  15.     rm -f nand_sdram.dis nand_sdram.bin nand_sdram_elf *.o
以下为能直接运行的二进制文件，下载到Nand Flash 的 Black0 直接以Nand Flash运行。
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