S3C2440 寄存器一种比较好的结构定义

有的时候我们在操作一组地址连续的寄存器组的时候，我们可以把他定义为一个结构体，这样就没有必要每次在程序写类似：

            #defind  XXXXX  *(volatile (unsigned int *)) 0x48000000

 

这样写很麻烦，当然你也可以单独写个头文件定义所有的头文件 ！

 

*********************************************************

S3C2440_Register_Base_Addr.h

*********************************************************

#ifndef _S3C2440_H_
#define _S3C2440_H_

#define UART_CHANNELS   3
#define SPI_CHANNELS    2

#define ECCSIZE         512
#define ECCBYTES        3

enum uarts_nr {
        UART0,
        UART1,
        UART2
};

#define MEMCTL_BASE             0x48000000
#define USB_HOST_BASE           0x49000000
#define INTERRUPT_BASE          0x4A000000
#define DMA_BASE                0x4B000000
#define CLOCK_POWER_BASE        0x4C000000
#define LCD_BASE                0x4D000000
#define NAND_BASE               0x4E000000
#define UART_BASE               0x50000000
#define TIMER_BASE              0x51000000
#define USB_DEVICE_BASE         0x52000140
#define WATCHDOG_BASE           0x53000000
#define I2C_BASE                0x54000000
#define I2S_BASE                0x55000000
#define GPIO_BASE               0x56000000
#define RTC_BASE                0x57000000
#define ADC_BASE                0x58000000
#define SPI_BASE                0x59000000
#define SDI_BASE                0x5A000000

#include

static inline struct memctl *get_base_memctl(void)
{
        return (struct memctl *)MEMCTL_BASE;
}
static inline struct usb_host *get_base_usb_host(void)
{
        return (struct usb_host *)USB_HOST_BASE;
}
static inline struct interrupt *get_base_interrupt(void)
{
        return (struct interrupt *)INTERRUPT_BASE;
}
static inline struct dmas *get_base_dmas(void)
{
        return (struct dmas *)DMA_BASE;
}
static inline struct clock_power *get_base_clock_power(void)
{
        return (struct clock_power *)CLOCK_POWER_BASE;
}
static inline struct lcd *get_base_lcd(void)
{
        return (struct lcd *)LCD_BASE;
}
static inline struct nand *get_base_nand(void)
{
        return (struct nand *)NAND_BASE;
}
static inline struct uart *get_base_uart(enum uarts_nr n)
{
        return (struct uart *)(UART_BASE + (n * 0x4000));
}
static inline struct timers *get_base_timers(void)
{
        return (struct timers *)TIMER_BASE;
}
static inline struct usb_device *get_base_usb_device(void)
{
        return (struct usb_device *)USB_DEVICE_BASE;
}
static inline struct watchdog *get_base_watchdog(void)
{
        return (struct watchdog *)WATCHDOG_BASE;
}
static inline struct i2c *get_base_i2c(void)
{
        return (struct i2c *)I2C_BASE;
}
static inline struct i2s *get_base_i2s(void)
{
        return (struct i2s *)I2S_BASE;
}

static inline struct gpio *get_base_gpio(void)
{
        return (struct gpio *)GPIO_BASE;
}

static inline struct rtc *get_base_rtc(void)
{
        return (struct rtc *)RTC_BASE;
}
static inline struct adc *get_base_adc(void)
{
        return (struct adc *)ADC_BASE;
}
static inline struct spi *get_base_spi(void)
{
        return (struct spi *)SPI_BASE;
}
static inline struct sdi *get_base_sdi(void)
{
        return (struct sdi *)SDI_BASE;
}

#endif

 

 

***************************************************

S3C2440_Register_Map.h

*************************************************** 

#ifndef _REGSTRUCT_H_
#define _REGSTRUCT_H_

typedef volatile unsigned char REG8;
typedef volatile unsigned short REG16;
typedef volatile unsigned int REG32;

struct memctl {
        REG32   BWSCON;
        REG32   BANKCON[8];
        REG32   REFRESH;
        REG32   BANKSIZE;
        REG32   MRSRB6;
        REG32   MRSRB7;
};

struct usb_host {
        REG32   HcRevision;
        REG32   HcControl;
        REG32   HcCommonStatus;
        REG32   HcInterruptStatus;
        REG32   HcInterruptEnable;
        REG32   HcInterruptDisable;
        REG32   HcHCCA;
        REG32   HcPeriodCuttendED;
        REG32   HcControlHeadED;
        REG32   HcControlCurrentED;
        REG32   HcBulkHeadED;
        REG32   HcBuldCurrentED;
        REG32   HcDoneHead;
        REG32   HcRmInterval;
        REG32   HcFmRemaining;
        REG32   HcFmNumber;
        REG32   HcPeriodicStart;
        REG32   HcLSThreshold;
        REG32   HcRhDescriptorA;
        REG32   HcRhDescriptorB;
        REG32   HcRhStatus;
        REG32   HcRhPortStatus1;
        REG32   HcRhPortStatus2;
};

struct interrupt {
        REG32   SRCPND;
        REG32   INTMOD;
        REG32   INTMSK;
        REG32   PRIORITY;
        REG32   INTPND;
        REG32   INTOFFSET;
        REG32   SUBSRCPND;
        REG32   INTSUBMSK;
};

struct dma {
        REG32   DISRC;
        REG32   DISRCC;
        REG32   DIDST;
        REG32   DIDSTC;
        REG32   DCON;
        REG32   DSTAT;
        REG32   DCSRC;
        REG32   DCDST;
        REG32   DMASKTRIG;
        REG32   res[7];
};

struct dmas {
        struct dma      dma[4];
};

struct clock_power {
        REG32   LOCKTIME;
        REG32   MPLLCON;
        REG32   UPLLCON;
        REG32   CLKCON;
        REG32   CLKSLOW;
        REG32   CLKDIVN;
        REG32   CAMDIVN;
};

struct lcd {
        REG32   LCDCON1;
        REG32   LCDCON2;
        REG32   LCDCON3;
        REG32   LCDCON4;
        REG32   LCDCON5;
        REG32   LCDSADDR1;
        REG32   LCDSADDR2;
        REG32   LCDSADDR3;
        REG32   REDLUT;
        REG32   GREENLUT;
        REG32   BLUELUT;
        REG32   res[8];
        REG32   DITHMODE;
        REG32   TPAL;
        REG32   LCDINTPND;
        REG32   LCDSRCPND;
        REG32   LCDINTMSK;
        REG32   LPCSEL;
};

struct nand {
        REG32   NFCONF;
        REG32   NFCONT;
        REG32   NFCMD;
        REG32   NFADDR;
        REG32   NFDATA;
        REG32   NFMECCD0;
        REG32   NFMECCD1;
        REG32   NFSECCD;
        REG32   NFSTAT;
        REG32   NFESTAT0;
        REG32   NFESTAT1;
        REG32   NFMECC0;
        REG32   NFMECC1;
        REG32   NFSECC;
        REG32   NFSBLK;
        REG32   NFEBLK;
};

struct uart {
        REG32   ULCON;
        REG32   UCON;
        REG32   UFCON;
        REG32   UMCON;
        REG32   UTRSTAT;
        REG32   UERSTAT;
        REG32   UFSTAT;
        REG32   UMSTAT;
        REG8    UTXH;
        REG8    res1[3];
        REG8    URXH;
        REG8    res2[3];
        REG32   UBRDIV;
};

struct timer {
        REG32   TCNTB;
        REG32   TCMPB;
        REG32   TCNTO;
};

struct timers {
        REG32           TCFG0;
        REG32           TCFG1;
        REG32           TCON;
        struct timer    ch[4];
        REG32           TCNTB4;
        REG32           TCNTO4;
};

struct usb_dev_fifos {
        REG8    EP_FIFO_REG;
        REG8    res[3];
};

struct usb_dev_dmas {
        REG8    EP_DMA_CON;
        REG8    res1[3];
        REG8    EP_DMA_UNIT;
        REG8    res2[3];
        REG8    EP_DMA_FIFO;
        REG8    res3[3];
        REG8    EP_DMA_TTC_L;
        REG8    res4[3];
        REG8    EP_DMA_TTC_M;
        REG8    res5[3];
        REG8    EP_DMA_TTC_H;
        REG8    res6[3];
};

struct usb_device {
        REG8    FUNC_ADDR_REG;
        REG8    res1[3];
        REG8    PWR_REG;
        REG8    res2[3];
        REG8    EP_INT_REG;
        REG8    res3[15];
        REG8    USB_INT_REG;
        REG8    res4[3];
        REG8    EP_INT_EN_REG;
        REG8    res5[15];
        REG8    USB_INT_EN_REG;
        REG8    res6[3];
        REG8    FRAME_NUM1_REG;
        REG8    res7[3];
        REG8    FRAME_NUM2_REG;
        REG8    res8[3];
        REG8    INDEX_REG;
        REG8    res9[7];
        REG8    MAXP_REG;
        REG8    res10[7];
        REG8    EP0_CSR_IN_CSR1_REG;
        REG8    res11[3];
        REG8    IN_CSR2_REG;
        REG8    res12[3];
        REG8    OUT_CSR1_REG;
        REG8    res13[7];
        REG8    OUT_CSR2_REG;
        REG8    res14[3];
        REG8    OUT_FIFO_CNT1_REG;
        REG8    res15[3];
        REG8    OUT_FIFO_CNT2_REG;
        REG8    res16[3];
        struct usb_dev_fifos    fifo[5];
        struct usb_dev_dmas     dma[5];
};

struct watchdog {
        REG32   WTCON;
        REG32   WTDAT;
        REG32   WTCNT;
};

struct i2c {
        REG32   IICCON;
        REG32   IICSTAT;
        REG32   IICADD;
        REG32   IICDS;
};

struct i2s {
        REG16   IISCON;
        REG16   res1;
        REG16   IISMOD;
        REG16   res2;
        REG16   IISPSR;
        REG16   res3;
        REG16   IISFCON;
        REG16   res4;
        REG16   IISFIFO;
        REG16   res5;
};

struct gpio {
        REG32   GPACON;
        REG32   GPADAT;
        REG32   res1[2];
        REG32   GPBCON;
        REG32   GPBDAT;
        REG32   GPBUP;
        REG32   res2;
        REG32   GPCCON;
        REG32   GPCDAT;
        REG32   GPCUP;
        REG32   res3;
        REG32   GPDCON;
        REG32   GPDDAT;
        REG32   GPDUP;
        REG32   res4;
        REG32   GPECON;
        REG32   GPEDAT;
        REG32   GPEUP;
        REG32   res5;
        REG32   GPFCON;
        REG32   GPFDAT;
        REG32   GPFUP;
        REG32   res6;
        REG32   GPGCON;
        REG32   GPGDAT;
        REG32   GPGUP;
        REG32   res7;
        REG32   GPHCON;
        REG32   GPHDAT;
        REG32   GPHUP;
        REG32   res8;
        REG32   MISCCR;
        REG32   DCLKCON;
        REG32   EXTINT0;
        REG32   EXTINT1;
        REG32   EXTINT2;
        REG32   EINTFLT0;
        REG32   EINTFLT1;
        REG32   EINTFLT2;
        REG32   EINTFLT3;
        REG32   EINTMASK;
        REG32   EINTPEND;
        REG32   GSTATUS0;
        REG32   GSTATUS1;
        REG32   GSTATUS2;
        REG32   GSTATUS3;
        REG32   GSTATUS4;
        REG32   res9[3];
        REG32   MSLCON;
        REG32   GPJCON;
        REG32   GPJDAT;
        REG32   GPJUP;
};

struct rtc {
        REG8    res0[64];
        REG8    RTCCON;
        REG8    res1[3];
        REG8    TICNT;
        REG8    res2[11];
        REG8    RTCALM;
        REG8    res3[3];
        REG8    ALMSEC;
        REG8    res4[3];
        REG8    ALMMIN;
        REG8    res5[3];
        REG8    ALMHOUR;
        REG8    res6[3];
        REG8    ALMDATE;
        REG8    res7[3];
        REG8    ALMMON;
        REG8    res8[3];
        REG8    ALMYEAR;
        REG8    res9[3];
        REG8    RTCRST;
        REG8    res10[3];
        REG8    BCDSEC;
        REG8    res11[3];
        REG8    BCDMIN;
        REG8    res12[3];
        REG8    BCDHOUR;
        REG8    res13[3];
        REG8    BCDDATE;
        REG8    res14[3];
        REG8    BCDDAY;
        REG8    res15[3];
        REG8    BCDMON;
        REG8    res16[3];
        REG8    BCDYEAR;
        REG8    res17[3];
};

struct adc {
        REG32   ADCCON;
        REG32   ADCTSC;
        REG32   ADCDLY;
        REG32   ADCDAT0;
        REG32   ADCDAT1;
        REG32   ADCUPDN;
};

struct spi_channel {
        REG8    SPCON;
        REG8    res1[3];
        REG8    SPSTA;
        REG8    res2[3];
        REG8    SPPIN;
        REG8    res3[3];
        REG8    SPPRE;
        REG8    res4[3];
        REG8    SPTDAT;
        REG8    res5[3];
        REG8    SPRDAT;
        REG8    res6[3];
        REG8    res7[16];
};

struct spi {
        struct spi_channel      ch[SPI_CHANNELS];
};

struct s3c2400_mmc {
        REG8    MMCON;
        REG8    res1[3];
        REG8    MMCRR;
        REG8    res2[3];
        REG8    MMFCON;
        REG8    res3[3];
        REG8    MMSTA;
        REG8    res4[3];
        REG16   MMFSTA;
        REG16   res5;
        REG8    MMPRE;
        REG8    res6[3];
        REG16   MMLEN;
        REG16   res7;
        REG8    MMCR7;
        REG8    res8[3];
        REG32   MMRSP[4];
        REG8    MMCMD0;
        REG8    res9[3];
        REG32   MMCMD1;
        REG16   MMCR16;
        REG16   res10;
        REG8    MMDAT;
        REG8    res11[3];
};

struct sdi {
        REG32   SDICON;
        REG32   SDIPRE;
        REG32   SDICARG;
        REG32   SDICCON;
        REG32   SDICSTA;
        REG32   SDIRSP0;
        REG32   SDIRSP1;
        REG32   SDIRSP2;
        REG32   SDIRSP3;
        REG32   SDIDTIMER;
        REG32   SDIBSIZE;
        REG32   SDIDCON;
        REG32   SDIDCNT;
        REG32   SDIDSTA;
        REG32   SDIFSTA;
        REG8    SDIDAT;
        REG8    res[3];
        REG32   SDIIMSK;
};

#endif