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guangmangdz

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mtkop mt7688/28 3uart is ok 简单记录

分类： LINUX

2015-08-16 21:53:39

使用quilt打了一个patch，原本patch最高到0307.我这个则起名为0308-to-mt7688-3uart.patch
0308-to-mt7688-3uart.7z
除了打patch外，还需要做两件事，
1.kernel_menucofnig,    one port only
2.kernel_menuconfig,    将串口数量改为3                                         
接下来，3个串口全部可用，值得一提的是，uart2是映射到GPIO18和GPIO19上。                                                

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  1. --- a/arch/mips/ralink/cmdline.c
  2. +++ b/arch/mips/ralink/cmdline.c
  3. @@ -43,7 +43,7 @@
  4.  
  5.  #if defined (CONFIG_RT2880_ROOTFS_IN_FLASH)
  6.  #ifdef CONFIG_SYSFS
  7. -char rt2880_cmdline[]="console=ttyS1,57600n8 root=/dev/mtdblock5";
  8. +char rt2880_cmdline[]="console=ttyS0,57600n8 root=/dev/mtdblock5";
  9.  #else
  10.  char rt2880_cmdline[]="console=ttyS1,57600n8 root=1f05";
  11.  #endif
  12. --- a/arch/mips/ralink/init.c
  13. +++ b/arch/mips/ralink/init.c
  14. @@ -635,7 +635,7 @@ void prom_init_sysclk(void)
  15.  ** To get the correct baud_base value, prom_init_sysclk() must be called before
  16.  ** this function is called.
  17.  */
  18. -static struct uart_port serial_req[2];
  19. +static struct uart_port serial_req[3];
  20.  __init int prom_init_serial_port(void)
  21.  {
  22.  
  23. @@ -647,7 +647,7 @@ __init int prom_init_serial_port(void)
  24.  
  25.    serial_req[0].type = PORT_16550A;
  26.    serial_req[0].line = 0;
  27. - serial_req[0].irq = SURFBOARDINT_UART;
  28. + serial_req[0].irq = SURFBOARDINT_UART_LITE1;
  29.    serial_req[0].flags = UPF_FIXED_TYPE;
  30.  #if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
  31.    serial_req[0].uartclk = 40000000;
  32. @@ -663,12 +663,12 @@ __init int prom_init_serial_port(void)
  33.    serial_req[0].iotype = UPIO_AU;
  34.  #endif
  35.    serial_req[0].regshift = 2;
  36. - serial_req[0].mapbase = RALINK_UART_BASE;
  37. - serial_req[0].membase = ioremap_nocache(RALINK_UART_BASE, PAGE_SIZE);
  38. + serial_req[0].mapbase = RALINK_UART_LITE1_BASE;
  39. + serial_req[0].membase = ioremap_nocache(RALINK_UART_LITE1_BASE, PAGE_SIZE);
  40.  
  41.    serial_req[1].type = PORT_16550A;
  42.    serial_req[1].line = 1;
  43. - serial_req[1].irq = SURFBOARDINT_UART1;
  44. + serial_req[1].irq = SURFBOARDINT_UART_LITE2;
  45.    serial_req[1].flags = UPF_FIXED_TYPE;
  46.  #if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
  47.    serial_req[1].uartclk = 40000000;
  48. @@ -684,11 +684,22 @@ __init int prom_init_serial_port(void)
  49.    serial_req[1].iotype = UPIO_AU;
  50.  #endif
  51.    serial_req[1].regshift = 2;
  52. - serial_req[1].mapbase = RALINK_UART_LITE_BASE;
  53. - serial_req[1].membase = ioremap_nocache(RALINK_UART_LITE_BASE, PAGE_SIZE);
  54. + serial_req[1].mapbase = RALINK_UART_LITE2_BASE;
  55. + serial_req[1].membase = ioremap_nocache(RALINK_UART_LITE2_BASE, PAGE_SIZE);
  56. + /* added by mango 20150811 */
  57. + serial_req[2].type = PORT_16550A;
  58. + serial_req[2].line = 2;
  59. + serial_req[2].irq = SURFBOARDINT_UART_LITE3;
  60. + serial_req[2].flags = UPF_FIXED_TYPE;
  61. + serial_req[2].uartclk = 40000000;
  62. + serial_req[2].iotype = UPIO_MEM32;
  63. + serial_req[2].regshift= 2;
  64. + serial_req[2].mapbase = RALINK_UART_LITE3_BASE;
  65. + serial_req[2].membase = ioremap_nocache(RALINK_UART_LITE3_BASE,PAGE_SIZE);
  66.  
  67.    early_serial_setup(&serial_req[0]);
  68.    early_serial_setup(&serial_req[1]);
  69. + early_serial_setup(&serial_req[2]);
  70.  
  71.    return(0);
  72.  }
  73. @@ -751,6 +762,14 @@ static void serial_setbrg(unsigned long
  74.          DLM(RALINK_SYSCTL_BASE + 0x500) = clock_divisor >> 8;
  75.          LCR(RALINK_SYSCTL_BASE + 0x500) = UART_LCR_WLEN8;
  76.  #endif
  77. +/*mango*/
  78. + IER(RALINK_SYSCTL_BASE + 0xE00) = 0;
  79. + FCR(RALINK_SYSCTL_BASE + 0xE00) = 0;
  80. + LCR(RALINK_SYSCTL_BASE + 0xE00) = (UART_LCR_WLEN8 | UART_LCR_DLAB);
  81. + DLL(RALINK_SYSCTL_BASE + 0xE00) = clock_divisor & 0xff;
  82. + DLM(RALINK_SYSCTL_BASE + 0xE00) = clock_divisor >> 8;
  83. + LCR(RALINK_SYSCTL_BASE + 0xE00) = UART_LCR_WLEN8;
  84. +
  85.  }
  86.  
  87.  
  88. --- a/drivers/char/ralink_gpio.c
  89. +++ b/drivers/char/ralink_gpio.c
  90. @@ -2459,7 +2459,7 @@ int __init ralink_gpio_init(void)
  91.  {
  92.      unsigned int i;
  93.      u32 gpiomode;
  94. -
  95. +    u32 agpio_cfg=0;
  96.  #ifdef CONFIG_DEVFS_FS
  97.      if (devfs_register_chrdev(ralink_gpio_major, RALINK_GPIO_DEVNAME,
  98.                  &ralink_gpio_fops)) {
  99. @@ -2492,7 +2492,22 @@ int __init ralink_gpio_init(void)
  100.      gpiomode &= ~0x2000; //clear bit[13] WLAN_LED
  101.  #endif
  102.      gpiomode |= RALINK_GPIOMODE_DFT;
  103. +    gpiomode &=~(0x03<<26);//clear bit[27][26] uart2
  104.      *(volatile u32 *)(RALINK_REG_GPIOMODE) = cpu_to_le32(gpiomode);
  105. + /* added by mango 20150811 for AGPIO_MODE init */
  106. +#if 0
  107. + agpio_cfg = le32_to_cpu(*(volatile u32 *)(RALINK_SYSCTL_ADDR+0x3C));
  108. + /* I2S bit3:0;1111:digital*/
  109. + agpio_cfg |=0x0f;
  110. + /* refclko bit4;1:digital */
  111. + agpio_cfg |=0x01<<4;
  112. + /* wled_OD_EN */
  113. + /* ephy p0 */
  114. + /* EPHY_GPIO_AIO_EN bit20:17;1111:digital */
  115. + agpio_cfg |=0x0f<<17;
  116. + *(volatile u32 *)(RALINK_SYSCTL_ADDR+0X3c) = cpu_to_le32(agpio_cfg);
  117. + printk("\n\r agpio_cfg");
  118. +#endif
  119.  
  120.      //enable gpio interrupt
  121.      *(volatile u32 *)(RALINK_REG_INTENA) = cpu_to_le32(RALINK_INTCTL_PIO);
  122. --- a/drivers/char/ralink_gpio.h
  123. +++ b/drivers/char/ralink_gpio.h
  124. @@ -479,7 +479,7 @@
  125.  #define RALINK_GPIOMODE_SPI_SLAVE    0x4
  126.  #define RALINK_GPIOMODE_SPI_CS1        0x10
  127.  #define RALINK_GPIOMODE_I2S        0x40
  128. -#define RALINK_GPIOMODE_UART1        0x100
  129. +#define RALINK_GPIOMODE_UART1        0x000
  130.  #define RALINK_GPIOMODE_SDXC        0x400
  131.  #define RALINK_GPIOMODE_SPI        0x1000
  132.  #define RALINK_GPIOMODE_WDT        0x4000
  133. @@ -489,8 +489,8 @@
  134.  #define RALINK_GPIOMODE_EPHY        0x40000
  135.  #define RALINK_GPIOMODE_P0LED        0x100000
  136.  #define RALINK_GPIOMODE_WLED        0x400000
  137. -#define RALINK_GPIOMODE_UART2        0x1000000
  138. -#define RALINK_GPIOMODE_UART3        0x4000000
  139. +#define RALINK_GPIOMODE_UART2        0x0000000
  140. +#define RALINK_GPIOMODE_UART3        0x0000000
  141.  #define RALINK_GPIOMODE_PWM0        0x10000000
  142.  #define RALINK_GPIOMODE_PWM1        0x40000000
  143.  
  144. @@ -505,7 +505,7 @@
  145.  #elif defined (CONFIG_RALINK_MT7620)
  146.  #define RALINK_GPIOMODE_DFT        (RALINK_GPIOMODE_I2C)
  147.  #elif defined (CONFIG_RALINK_MT7628)
  148. -#define RALINK_GPIOMODE_DFT        (RALINK_GPIOMODE_UART2 | RALINK_GPIOMODE_UART3) | (RALINK_GPIOMODE_SPI_CS1) | (RALINK_GPIOMODE_WDT)
  149. +#define RALINK_GPIOMODE_DFT        (RALINK_GPIOMODE_UART2 | RALINK_GPIOMODE_UART3 | RALINK_GPIOMODE_UART1 | RALINK_GPIOMODE_SPI_CS1 | RALINK_GPIOMODE_WDT | RALINK_GPIOMODE_SPI_SLAVE )
  150.  #else
  151.  #define RALINK_GPIOMODE_DFT (RALINK_GPIOMODE_UARTF)
  152.  #endif      
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