online Verilog-1995 Quick Reference Guide（二)

Operators perform an operation on one or two operands:

Unary expressions

operator operand

Binary expressions

operand operator operand

The operands may be either net or register data types. Operands may be scalar, vector, or bit selects of a vector. Operators which return a true/false result will return a 1-bit value where 1 is true, 0 is false, and X is indeterminate.

 

	Usage	Description
Arithmetic Operators
+	m + n	Add n to m
-	m - n	Subtract n from m
-	-m	Negate m (2's complement)
*	m * n	Multiply m by n
/	m / n	Divide m by n
%	m % n	Modulus of m / n
Bitwise Operators
~	~m	Invert each bit of m
&	m & n	AND each bit of m with each bit of n
|	m | n	OR each bit of m with each bit of n
^	m ^ n	Exclusive OR each bit of m with n
~^ ^~	m ~^ n m ^~ n	Exclusive NOR each bit of m with n
Unary Reduction Operators
&	&m	AND all bits in m together (1-bit result)
~&	~&m	NAND all bits in m together (1-bit result)
|	|m	OR all bits in m together (1-bit result)
~|	~|m	NOR all bits in m together (1-bit result)
^	^m	Exclusive OR all bits in m (1-bit result)
~^ ^~	~^m ^~m	Exclusive NOR all bits in m (1-bit result)
Logical Operators
!	!m	Is m not true? (1-bit True/False result)
&&	m && n	Are both m and n true? (1-bit True/False result)
||	m || n	Are either m or n true? (1-bit True/False result)
Equality Operators (compares logic values of 0 and 1
==	m == n	Is m equal to n? (1-bit True/False result)
!=	m != n	Is m not equal to n? (1-bit True/False result)
Identity Operators (compares logic values of 0, 1, X and Z
===	m === n	Is m identical to n? (1-bit True/False results)
!==	m !== n	Is m not identical to n? (1-bit True/False result)
Relational Operators
<	m < n	Is m less than n? (1-bit True/False result)
>	m > n	Is m greater than n? (1-bit True/False result)
<=	m <= n	Is m less than or equal to n? (True/False result)
>=	m >= n	Is m greater than or equal to n? (True/False result)
Logical Shift Operators
<<	m << n	Shift m left n-times
>>	m >> n	Shift m right n-times
Miscellaneous Operators
? :	sel?m:n	If sel is true, select m: else select n
{}	{m,n}	Concatenate m to n, creating larger vector
{{}}	{n{m}}	Replicate m n-times
->	-> m	Trigger an event on an event data type

 

Operator Precedence
! ~ + - (unary) * / % + - (binary) << >> < <= > >= == != === !== & ~& ^ ~^ | ~| && || ?:	highest precedence lowest precedence

 

Syntax

Explicit Continuous Assignment

 [size] net_name;
assign #() net_name = expression;

Implicit Continuous Assignment

 () [size] net_name = expression;

	Explicit continuous assignments require two statements: one to declare the net, and one to continuously assign a value to it.
	Implicit continuous assignments combine the net declaration and continuous assignment into one statement.
	may be any of the net data types except trireg.
	(optional) may only be specified when the continuous assignment is combined with a net declaration. The default strength is (strong1, strong0).
	(optional) follows the same syntax as . The default is zero delay.
	may include any data type, any operator, and calls to functions.
	Continuous assignments model combinational logic. Each time a signal changes on the right-hand side, the right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.
	Continuous assignments are declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances.

 

Continuous Assignment Examples

//A 32-bit wide 2:1 MUX
wire [31:0] mux_out;
assign mux_out = sel? a : b;
    

//A 16-bit wide tri-state buffer with delay
tri [0:15] #2.8 buf_out = en? in: 16'bz;
    

//A 64-bit ALU with ECL output strengths
wire [63:0] (strong1,pull0) alu_out = alu_function(opcode,a,b);
    

 

Syntax

task task_name;
   input, output, and inout declarations
   local variable declarations
   procedural_statement or statement_group
endtask
    

 

Tasks are subroutines.

	May have any number of inputs, outputs or inouts.
	May contain timing controls (#, @, or wait).

 

Example of a Task

task read_mem;                 //TASK DEFINITION
  input [15:0] address;          //declaration order
  output [31:0] data;            // determines order
  begin                          // of arguments when
    read_request = 1;            // task is called
    wait (read_grant) addr_bus = address;
    data = data_bus;
    #5 addr_bus = 16'bz; read_request = 0;
  end
endtask
    

read_mem(PC, IR);              //TASK CALL
    

 

Syntax

function [] function_name;
   input declarations
   local variable declarations
   procedural_statement or statement_group
endfunction
    

 

Functions return the value that is assigned to the function name.

	Must have at least one input; may not have outputs or inouts.
	May not contain timing controls (#, @, or wait).
	(optional) is the return bit range as [msb:lsb], or the keywords integer or real. The default size is 1-bit.

 

Example of a Function

function [7:0] GetByte;        //FUNCTION DEFINITION
  input [63:0] Word;             //declaration order
  input [3:0] ByteNum;           //determines order
  integer Bit;                   //of arguments when
  reg [7:0] temp;                //called
  begin
    for (Bit=0; Bit<=7; Bit=Bit+1)
    temp[Bit] = Word[((ByteNum-1)*8)+Bit];
    GetByte = temp;              //A function returns
  end                            // the value assigned
endfunction                      // to its name
    

this_byte = GetByte(data,4);   //FUNCTION CALL
    

 

Syntax

specify
   
   
   
   
   
endspecify
    

 

specparam param_name = value, param_name = value, ...;

	specparams are constants used to store delays, delay calculation factors, synthesis factors, etc.
	value may be interger, real, delay, or quoted string.

Timing constraint checks are system tasks that model restrictions on input changes, such as setup times and hold times.

Timing Check Syntax

$setup(, , , );
$hold(, , , );
$setuphold(, , , , );
$skew(, , , );
$recovery(, , , );
$period(, , );
$width(, , , );

	Timing checks may only be used in specify blocks.
	The  is and edge of an input signal that establishes a reference point for changes on the data event.
	The  is the input signal that is monitored for changes.
	The data_event and reference_event signals must be module input ports.
	The  and  are delay values and use the same syntax as single .
	The  (optional) is a reg variable used as a flag. When a timing violation occurs, the model functionality can use the notifier flag to modify the model outputs.

 

:

(input_port : output_port) = ();

:

( input_port  (output_port :)) = ();

	(optional) may be either posedge or negedge. If not specified, all input transitions are used.
	(optional) is the input port or value the output will receive. The source is ignored by most logic simulators, but may be used by timing analyzers.

:

if () simple_or_edge-sensitive_path_delay
if () simple_or_edge-sensitive_path_delay
ifnone simple_path_delay

	Allows different delays for the same path to be specified, based on other input conditions.
	may only be based on input ports.
	Most operators may be used with the condition, but should resolve to true/false (a logic X or Z is considered true; if the condition resolves to a vector, only the lsb is used).
	Each state-dependent delay for the same path must have a different condition or a different edge-sensitive edge.
	The ifnone condition (optional) may only be a simple path delay, and serves as a default if no other condition evaluates as true.

 (optional) is either + or D, and indicates whether-or-not the input will be inverted. The polarity token is ignored by most logic simulators, but may be used by timing analyzers.  is either *> for full connection or => for parallel connection.

	Full connection path delay indicates every input bit may have a delay path to every output bit.
	Parallel connection path delay indicates each input bit is connected to its corresponding output bit (bit 0 to bit 0, bit 1 to bit 1, ...)

 can represent 1, 2, 3, 6 or 12 transitions may be specified. Each transition may have a single delay or a min:typ:max delay range.

Delays	Transitions represented (in order)
1	all output transitions
2	rise, fall output transitions
3	rise, fall, turn-off output transitions
6	rise, fall, 0->Z, Z->1, 1->Z, Z->0
12	rise, fall, 0->Z, Z->1, 1->Z, Z->0, 0->X, X->1, 1->X, X->0, X->Z, Z->X

 

Specify Block Examples	Notes
(a => b) = 1.8;	parallel connection path; one delay for all output transitions
(a -*> b) = 2:3:4;	full connection path; one min:typ:max delay range for all output transitions; b receives the inverted value of a
specparam t1 = 3:4:6, t2 = 2:3:4; (a => y) = (t1,t2);	different path delays for rise, fall transitions
(a *> y1,y2) = (2,3,4,3,4,3);	different delays for 6 output transitions
(posedge clk => (qb -: d)) = (2.6, 1.8);	edge-sensitive path delay; timing path is positive edge of clock to qb; qb receives the inverted value of data
if (rst && pst) (posedge clk=>(q +: d))=2;	state-dependent edge sensitive path delay
if (opcode = 3'b000) (a,b *> o) = 15; if (opcode = 3'b001) (a,b *> o) = 25; ifnone (a,b *> o) = 10;	state-dependent path delays; an ALU with different delays for certain operations (default delay has no condition)

 

 

Syntax

primitive primitive_name (output, input, input, ... );
  output terminal_declaration;
  input terminal_declaration;
  reg output_terminal;
  initial output_terminal = logic_value;
  table
    table_entry;
    table_entry;
  endtable
endprimitive

 

User Defined Primitives define new primitives, which are used exactly the same as built-in primitives.

	All terminals must be scalar (1-bit).
	Only one output is allowed, which must be the first terminal.
	The maximum number of inputs is at least 9 inputs for a sequential UDP and 10 inputs for a combinational UDP.
	Logic levels of 0, 1, X and transitions between those values may be represented in the table. The logic value Z is not supported with UDPs.
	reg declaration (optional) defines a sequential UDP by creating internal storage. Only the output may be a reg.
	initial (optional) is used to define the initial (power-up) state for sequential UDP's. Only the logic values 0, 1, and X may be used. The default state is X.

16.1 UDP Table Entries

input_logic_values : output_logic_value ;

Combinational logic table entry. Only logic level values may be specified (0, 1, X and don't care).

input_logic_values : previous_state : output_logic_value ;

Sequential logic table entry. May only be used when the output is also declared as a reg data type. Both input logic level and input logic transition values may be specified.

	A white space must separate each input value in the table.
	The input values in the table must be listed in the same order as the terminal list in the primitive statement.
	Any combination of input values not specified in the table will result in a logic X (unknown) value on the output.
	Only one signal may have an edge transition specified for each entry in the table.
	If an edge transition is specified for one input, the UDP becomes sensitive to transitions on all inputs. Therefore, all other inputs must have table entries to cover transitions, or when the transition occurs the UDP will output an X.
	Level sensitive table entries have precedence over edge sensitive table entries.

16.2 UDP Table Symbols

 

Truth Table Symbol	Definition
0	logic 0 on input or output
1	logic 1 on input or output
x or X	unknown on input or output
-	no change on output (may only be used with sequential UDPs)
?	don't care if an input is 0, 1, or X
b or B	don't care if and input is 0 or 1
(vw)	input transition from logic v to logic w e.g.: (01) represents transition from 0 to 1
r or R	rising input transition: same as (01)
f or F	falling input transition: same as (10)
p or P	positive input transition: (01), (0X) or (X1)
n or N	negative input transition: (10), (1X) or (X0)
*	any possible input transition: same as (??)

 

 

UDP Examples

primitive mux (y, a, b, sel); //COMBINATIONAL UDP
  output y;
  input sel, a, b;
  table  //table order for inputs matches primitive statement
  // a  b  sel : y
     0  ?   0  : 0;  //select a; don't care about b
     1  ?   0  : 1;  //select a; don't care about b
     ?  0   1  : 0;  //select b; don't care about a
     ?  1   1  : 1;  //select b; don't care about a
  endtable
endprimitive

primitive dff (q,d,clk,rst); //SEQUENTIAL UDP
  output q;
  input clk, rst, d;
  reg q; //declaring output as reg defines
         //sequential device with an internal
         //storage state
  initial q = 0; //powers up in reset state
  table
  // d  clk rst:state:q
     ?   ?   0 :  ?  :0; //low true reset
     0   R   1 :  ?  :0; //clock in a 0
     1   R   1 :  ?  :1: //clock in a 1
     ?   N   1 :  ?  :-; //ignore negedge of clk
     *   ?   1 :  ?  :-; //ignore all edges on d
     ?   ?   P :  ?  :-; //ignore posedge of rst
     0 (0X)  1 :  0  :-; //reduce pessimism
     1 (0X)  1 :  1  :-; //reduce pessimism
    endtable
 endprimitive

 

Following is a list of Verilog HDL constructs supported by most synthesis tools.

	This list is not specific to any one tool - each synthesis tool supports a unique subset of the Verilog language.
	The constructs listed in this section represent a subset of the Verilog HDL that are supported by most synthesis tools.
	Verilog constructs not listed in this section may be supported by some synthesis tools - refer to the specific synthesis tool documentation.

Verilog HDL Constructs

Notes

module declarations

both module and macromodule keywords fully supported

port declarations
input output inout

fully supported; any vector size supported

net data types
wire wand wor
supply0 supply1

scalars and vectors fully supported

register data types
reg integer

register variables:

	may be scalar or vector or register array
	may be restricted to only making assignments to a register from just one procedure
	integers default to 32 bits

parameter constants

limited to integers; parameter redefinition may not be supported

module instances

fully supported; both port order and port name instantiation supported

primitive instances
and nand or nor
xor buf not
bufif1 bufif0
notif1 notif0

only gate primitives are supported

assign
continuous assignment

fully supported; both explicit and implicit forms supported

function definitions

may only use supported constructs; must be defined before being referenced

task definitions

may only use supported constructs; must be defined before being referenced

always procedural block

must have a sensitivity list

begin--end
statement groups

fully supported; named and unnamed blocks supported

disable statement group

must be used within the same named block that is being disabled

= blocking procedural assignment
<= non-blocking procedural assignment

fully supported; may be restricted to using only one type of assignment for all assignments to the same register variable

assign procedural continuous assignment

fully supported; the deassign keyword may not be supported

integer values

fully supported; all sizes and bases

if if-else
case casex casez
decision statements

logic X and Z only supported as don't care bits

for loops

the step assignment must be an increment or decrement (+ -)

while loops
forever loops

loop must take one clock cycle for each loop cycle (i.e.: an @(posedge clk) or @(negedge clk) must be within the loop)

operators
& ~& | ~| ^ ^~ ~^
== != < > <= =>
! && ||
<< >> {} {{}} ?:
+ - * /

operands may be:

	scalar or vector
	constant or variable
	The divisor for divide operator may be restricted to constants and a power of 2
	the === and !== operators are not supported

vector bit selects
vector part selects

fully supported on the right-hand side of an assignment; restricted to constant bit or part selects on the left-hand side of an assignment

 

EDA tool vendors and tool users may define tasks and functions specific to their tool, such as text output or waveform displays.

	System tasks and functions begin with the $ (dollar sign).
	Users may define additional built-in tasks and functions using the Verilog Programming Language Interface (PLI).
	A few of the most common system tasks and functions are listed in this section.

 

Text Formatting Codes
%b %o %d %h %e %f %t	binary values octal values decimal values hex values real values-exponential real values-decimal formatted time values	%s %m \t \n \" \\ %%	character strings hierarchical names print a tab print a newline print a quote print a backslash print a percent sign
A zero in format codes (e.g.: %0d) displays the value using the minimum field width required. The %e and %f may specify the field width for both sides of the decimal point (e.g.: %5.2f)

$monitor("text_with_format_specifiers", signal, signal, ... );

Invokes a background process that continuously monitors the signals listed, and prints the formatted message whenever one of the signals changes. A newline is automatically added to the text printed.

$display("text_with_format_specifiers", signal, signal, ... );

Prints the formatted message once when the statement is executed during simulation. A newline is automatically added to the text printed.

$write("text_with_format_specifiers", signal, signal, ... );

Like $display statement, except that no newline is added.

$strobe("text_with_format_specifiers", signal, signal, ... );

Like the $display statement, except that the printing of the text is delayed until all simulation events in the current time step have executed.

 = $fopen("file_name");

A function that opens a disk file for writing, and returns a 32-bit integer multi-channel-descriptor (mcd) pointer to the file.

$fclose();

A function that closes a disk file that was opened by $fopen.

$monitor(, "text_with_format_specifiers", signal, signal, ... );
$display(, "text_with_format_specifiers", signal, signal, ... );
$write(, "text_with_format_specifiers", signal, signal, ... );
$strobe(, "text_with_format_specifiers", signal, signal, ... );

Variations of the text display tasks that write to files which have been opened with $fopen.

$time

Returns the current simulation time as a 64-bit integer.

$stime

Returns the lower 32-bits of simulation time as an integer.

$realtime

Returns the current simulation time as a real number.

$timeformat(unit, precision, "suffix", min_field_width);

Controls the format used by the %t text format specifier.

	unit is the base that time is to be displayed in, from 0 to -15
	precision is the number of decimal points to display.
	suffix is a string appended to the time, such as " ns".
	min_field_width is the minimum number of characters that will be displayed.

0 = 1 sec -1 = 100 ms -2 = 10 ms -3 = 1 ms

-4 = 100 us -5 = 10 us -6 = 1 us

-7 = 100 ns -8 = 10 ns -9 = 1 ns

-10 = 100 ps -11 = 10 ps -12 = 1 ps

-13 = 100 fs -14 = 10 fs -15 = 1 fs

Example: $timeformat(-9, 2, " ns", 10);

$printtimescale(module_hierarchical_name);

Prints the time scale of the specified module, or the scope from which it is called if no module is specified.

$random(seed);

Returns a random 32-bit signed integer.

$readmemb("file_name", register_array, start, end);
$readmemh("file_name", register_array, start, end);

Opens a file for reading, and loads the contents into a register memory array. The file must be an ASCII file with values represented in binary ($readmemb) or hex ($readmemh). The start and end address values are optional.

$finish;

Finishes a simulation and exits the simulation process.

$stop;

Halts a simulation and enters an interactive debug mode.

 

Compiler directives provide a method for EDA tool vendors to control how their tool will interpret Verilog HDL models.

	Compiler directives begin with the grave accent character ( ` ).
	Compiler directives are not Verilog HDL statements; there is no semi-colon at the end of compiler directives.
	Compiler directives are not bound by modules or by files. When a tool encounters a compiler directive, the directive remains in effect until another compiler directive either modifies it or turns it off.
	A few of the most common compiler directives are listed in this section.

`reset_all

Resets all compiler directives that have a default back to the default. Directives that have no default are not affected.

`timescale time_unit base / precision base

Specifies the time units and precision for delays:

	time_unit is the amount of time a delay of 1 represents. The time unit must be 1 10 or 100
	base is the time base for each unit, ranging from seconds to femtoseconds, and must be: s ms us ns ps or fs
	precision and base represent how many decimal points of precision to use relative to the time units.

Example: `timescale 1 ns / 10 ps
Indicates delays are in 1 nanosecond units with 2 decimal points of precision (10 ps is .01 ns).

Note: There is no default timescale in Verilog; delays are simply relative numbers
  until a timescale directive declares the units and base the numbers represent.

`define  text_string
`define macro_name (arguments) text_string (arguments)

Text substitution macro. Allows a text string to be defined as a macro name.

	text_string will be substituted in place of the macro_name where ever the macro name is used.
	text_string is terminated by a carriage return. The string must be on one line.
	arguments are evaluated before text is substituted.
	macro_name must also be preceded by the grave accent mark ( ` ) each time the macro name is used.
	Comments may be used. They are not substituted into the place of the macro name.

Examples:

   `define cycle 20 //clock period
   always #(`cycle/2) clk = ~clk;

   `define NAND(dval) nand #(dval)
   `NAND(3) i1 (y,a,b);
   `NAND(3:4:5) i2 (o,c,d);

`include "file_name"

File inclusion. The contents of another Verilog HDL source file is inserted where the `include directive appears.

`ifdef 
     verilog_source_code
`else
     verilog_source_code
`endif

Conditional compilation. Allows Verilog source code to be optionally included, based on whether or not macro_name has been defined using `define or an invocation option.

Examples:

   `ifdef RTL
      wire y = a & b;
   `else
      and #1 (y,a,b);
   `endif

`celldefine
`endcelldefine

Flags the Verilog source code between the two directives as a cell. Some tools, such as a delay calculator for an ASIC design, need to distinguish between a module that represents an ASIC cell and other modules in the design.

`default_nettype 

Changes the net data type to be used for implicit net declarations. Any of the net data types may be specified. By default, the implicit net data type is wire.

`unconnected_drive pull1
`unconnected_drive pull0
`nounconnected_drive

Determines what logic value will be applied to unconnected module inputs. The default is `nounconnected_drive, which floats unconnected inputs and nets to high impedance.

`delay_mode_zero
`delay_mode_unit
`delay_mode_path
`delay_mode_distributed

Specifies the simulation delay mode.

`uselib file=file dir=directory libext=extension

Specifies the Verilog source library file or directory in which the compiler should search for the definitions of modules or UDPs instantiated in a design. A `uselib directive with no arguments removes any preceding library search directives.

Examples:

   `uselib file=/models/rtl_lib
      ALU i1 (y1,a,b,op);   //RTL model
   `uselib dir=/models/gate_lib libext=.v
      ALU i2 (y2,a,b,op);   //Gate model
   `uselib   //turn off `uselib searching