online Verilog-1995 Quick Reference Guide（一）

online Verilog-1995 Quick Reference Guide（一）
by Stuart Sutherland of Sutherland HDL, Inc., Portland, Oregon, USA

copyright 1995, Sutherland HDL, Inc., all rights reserved.  Permission is granted to use this document for personal purposes only.$nbsp; You may not reproduce or distribute any portion of this document by any means without first obtaining permission from Sutherland HDL, Inc.
Professionally printed copies of this reference guides are available for purchase.  See for details.

Verilog HDL constructs that represent hierarchy scope are:

	( begin- end or fork- join)

Each scope has its own name space. An identifier name defined within a scope is unique to that scope. References to an identifier name will search first in the local scope, and then search upward through the scope hierarchy up to a module boundary.

2.0 Concurrency

The following Verilog HDL constructs are independent processes that are evaluated concurrently in simulation time:

always and assign attribute begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endattribute endcase endfunction

endmodule endprimitive endspecify endtable endtask event for force forever fork function highz0 highz1 if ifnone initial inout input integer join medium module

large macromodule nand negedge nmos nor not notif0 notif1 or output parameter pmos posedge primitive pull0 pull1 pulldown pullup rcmos real realtime

reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared signed small specify specparam strength strong0 strong1 supply0 supply1 table task time tran

tranif0 tranif1 tri tri0 tri1 triand trior trireg unsigned vectored wait wand weak0 weak1 while wire wor xnor xor

 

blanks, tabs, newlines (carriage return), formfeeds and EOF (end-of-file).

// begins a single line comment, terminated by a newline.

/* begins a multi-line comment, terminated by a */.

Verilog is case sensitive.

	Must begin with alphabetic or underscore characters a-z A-Z _
	May contain the characters a-z A-Z 0-9 _ and $
	May use any character by escaping with a backslash ( \ ) at the beginning of the identifier, and terminating with a white space.

Examples	Notes
adder	legal identifier name
XOR	uppercase identifier is unique from xor keyword
\reset*	an escaped identifier (must be followed by a white space)

 

The Verilog HDL has 4 logic values.

Logic Value	Description
0	zero, low, or false
1	one, high, or true
z or Z	high impedance (tri-stated or floating)
x or X	unknown or uninitialized

 

The Verilog HDL has 8 logic strengths: 4 driving, 3 capacitive, and high impedance (no strength).

Strength Level	Strength Name	Specification Keyword		Display Mnemonic
7	Supply Drive	supply0	supply1	Su0	Su1
6	Strong Drive	strong0	strong1	St0	St1
5	Pull Drive	pull0	pull1	Pu0	Pu1
4	Large Capacitive	large		La0	La1
3	Weak Drive	weak0	weak1	We0	We1
2	Med. Capacitive	medium		Me0	Me1
1	Small Capacitive	small		Sm0	Sm1
0	High Impedance	highz0	highz1	HiZ0	HiZ1

 

Syntax
size'base value	Sized integer in a specific radix (base)

	size (optional) is the number of bits in the number. Unsized integers default to at least 32-bits.
	'base (optional) represents the radix. The default base is decimal.

Base	Symbol	Legal Values
binary	b or B	0, 1, x, X, z, Z, ?, _
octal	o or O	0-7, x, X, z, Z, ?, _
decimal	d or D	0-9, _
hexadecimal	h or H	0-9, a-f, A-F, x, X, z, Z, ?, _

	The ? is another way of representing the Z logic value.
	An _ (underscore) is ignored (used to enhance readability).
	Values are expanded from right to left (lsb to msb).
	When size is less than value, the upper bits are truncated.
	When size is larger than value, and the left-most bit of value is 0 or 1, zeros are left-extended to fill the size.
	When size is larger than value, and the left-most bit of value is Z or X, the Z or X is left-extended to fill the size.

Examples	Size	Base	Binary Equivalent
10	unsized	decimal	0...01010 (32-bits)
'o7	unsized	octal	0...00111 (32-bits)
1'b1	1 bit	binary	1
8'Hc5	8 bits	hex	11000101
6'hF0	6 bits	hex	110000 (truncated)
6'hF	6 bits	hex	001111 (zero filled)
6'hZ	6 bits	hex	ZZZZZZ (Z filled)

 

Syntax
value.value	decimal notation
baseEexponent	scientific notation (the E is not case sensitive)

	Real numbers are limited to the values 0-9 and underscore.
	There must be a value on either side of the decimal point.

Examples	Notes
0.5	must have value on both sides of decimal point
3e4	3 times 104 (30000)
5.8E-3	5.8 times 10-3 (0.0058)

Verilog HDL models are represented as modules.

Syntax

Implicit Internal Connection

module module_name (port_name, port_name, ... );

endmodule

Explicit Internal Connection

module module_name (.port_name (signal_name ), .port_name (signal_name ), ... );

endmodule

	Implicit internal connections connect the port to an internal net or register of the same name.
	Explicit internal connections connect the port to an internal signal with a different name, or a bit select, part select, or concatenation of internal signals.
	The keyword macromodule is a synonym for module. Some EDA tools may optimize tool execution performance by flattening macromodule hierarchy.
	are:

Module functionality may be:

	Behavioral - modeled with procedural blocks or continuous assignment statements.
	Structural - modeled as a netlist of module instances or primitive instances.
	A combination of behavioral and structural.

Module definitions may not be nested. Instead, modules instantiate other modules. Module definitions may be expressed using. Each instance of a module may redefine the parameters to be unique to that instance. Module items may appear in any order, but port declarations and data type declarations should be listed before the ports or signals are referenced.

Syntax

 [] port_name, port_name, ... ;

 is declared as:

	input for scalar or vector input ports.
	output for scalar or vector output ports.
	inout for scalar or vector bi-directional ports.

 is a range from [ msb : lsb ] (most-significant-bit to least-significant-bit).

	The msb and lsb must be literal integers, integer parameters, or an expression that resolves to an integer constant.
	Either little-endian convention (the lsb is the smallest bit number) or big-endian convention (the lsb is the largest bit number) may be used.
	The maximum port size may be limited, but will be at least 256 bits.

 

Examples	Notes
input a,b,sel;	3 scalar ports
output [7:0] result;	little endian convention
inout [0:15] data_bus;	big endian convention
input [15:12] addr;	msb:lsb may be any integer
parameter word = 32; input [word-1:0] addr;	constant expressions may be used

 

Syntax

 [] variable_name , variable_name , ... ;

 [] memory_name [];

 [] #() net_name , net_name , ... ;

 () [] #() net_name =  ;

trireg () [] #(, ) net_name, net_name, ... ;

parameter constant_name = value, constant_name = value, ... ;

specparam constant_name = value, constant_name = value, ... ;

event event_name, event_name, ... ;

 (optional) may only be specified on net data types. The syntax is the same as .

 is a range from [msb : lsb] (most-significant-bit to least-significant-bit).

	The msb and lsb must be integers, integer parameters or an expression that resolves to an integer constant.
	Either little-endian convention (the lsb is the smallest bit number) or big-endian convention (the lsb is the largest bit number) may be used.
	The maximum vector size is at least 65,536 bits (216).

 is from [ first_address : last_address].

first_address and last_address must be integers, integer parameters, or an expression that resolves to integer.

	Either ascending or descending address order may be used.
	The maximum array size is at least 16,777,216 words (224).

 (optional) is specified as (strength1, strength0) or (strength0, strength1). See  for keywords.

 (optional) specifies the amount of time a trireg net will store a charge after all drivers turn-off, before decaying to logic X. The syntax is (rise_delay, fall_delay, decay_time). The default decay is infinite.

Keyword	Functionality
reg	unsigned variable of any bit size
integer	signed 32-bit variable
time	unsigned 64-bit variable
real or realtime	double-precision floating point variable

Register data types are used as variables in procedural blocks.

	Registers store logic values only (no logic strength).
	A register data type must be used when the signal is on the left-hand side of a procedural assignment.

Keyword	Functionality
wire or tri	Simple interconnecting wire
wor or trior	Wired outputs OR together
wand ortriand	Wired outputs AND together
tri0	Pulls down when tri-stated
tri1	Pulls up when tri-stated
supply0	Constant logic 0 (supply strength)
supply1	Constant logic 1 (supply strength)
trireg	Stores last value when tri-stated (capacitance strength)

Net data types connect structural components together.

	Nets transfer both logic values and logic strengths.
	A net data type must be used when:

	A signal is driven by the output of some device.
	A signal is also declared as an input port or inout port.
	A signal is on the left-hand side of a continuous assignment.

Other Types	Functionality
parameter	Run-time constant for storing integers, real numbers, time, delays, or ASCII strings. Parameters may be for each instance of a module.
specparam	Specify block constant for storing integers, real numbers, time, delays or ASCII strings
event	A momentary flag with no logic value or data storage. Often used for synchronizing concurrent activities within a module.

 

7.4 Data Type Declaration Examples

Data Type Examples	Notes
wire a, b, c;	3 scalar nets
tri1 [7:0] data_bus;	8-bit net, pulls-up when tri-stated
reg [1:8] result;	an 8-bit unsigned variable
reg [7:0] RAM [0:1023];	a memory array; 8-bits wide, with 1K of addresses
wire #(2.4,1.8) carry;	a net with rise, fall delays
wire (strong1,pull0) sum = a+b;	net with drive strength and a continuous assignment
trireg (small) #(0,0,35) ram_bit;	net with small capacitance and 35 time unit decay time

 

Syntax

Port Order Connections

module_name  [] (signal, signal, ... );

Port Name Connections

module_name  [] (.port_name(signal), (.port_name(signal),...);

Explicit Parameter Redefinition

defparam heirarchy_path.parameter_name = value;

Implicit Parameter Redefinition

module_name #(value) instance_name (signals);

 

A module may be instantiated using port order or port names.

	Port order instantiation lists signal connections in the same order as the port list in the module definition. Unconnected ports are designated by two commas with no signal listed.
	Port name instantiation lists the port name and signal connected to it, in any order.

 (required) is used to make multiple instances of the same module unique from one another.

 (optional) instantiates multiple modules, each instance connected to separate bits of a vector.

	The range is specified as [lhi:rhi] (left-hand-index to right-hand-index).
	If the bit width of a module port in the array is the same as the width of the signal connected to it, the full signal is connected to each instance of the module port.
	If the bit width of a module port is different than the width of the signal connected to it, each module port instance is connected to a part select of the signal, with the right-most instance index connected to the right-most part of the vector, and progressing towards the left.
	There must be the correct number of bits in each signal to connect to all instances (the signal size and port size must be multiples).

Parameters in a module may be redefined for each instance.

	Explicit redefinition uses a defparam statement with the parameter's hierarchical name.
	Implicit redefinition uses the # token as part of the module instantiation. Parameters must be redefined in the same order they are declared within the module.

 

Module Instance Examples

module reg4 (q, d, clock);
  output [3:0] q;
  input [3:0] d;
  input clock;
  wire [3:0] q, d;
  wire clock;
  
  //port order connection,2nd port not connected
  dff u1 (q[0], , d[0], clock);

  //port name connection, qb not connected
  dff u2 (.clk(clock),.q(q[1]),.data(d[1]));

  //explicit parameter redefine
  dff u3 (q[2], ,d[2], clock);
  defparam u3.delay = 3.2;

  //implicit parameter redefine
  dff #(2) u4 (q[3], , d[3], clock);
endmodule

module dff (q, qb, data, clk);
  output q, qb;
  input data, clk;

  parameter delay = 1; //default delay parameter

  dff_udp #(delay) (q, data, clk);
  not (qb, q);
endmodule

 

Array of Instances Example

module tribuf64bit (out, in, enable);
  output [63:0] out;
  input [63:0] in;
  input enable;
  wire [63:0] out, in;
  wire enable;
  
  //array of 8 8-bit tri-state buffers; each instance is connected
  //to 8-bit part selects of the 64-bit vectors; The scalar
  //enable line is connected to all instances

  tribuf8bit i[7:0] (out, in, enable);

endmodule

module tribuf8bit (out, in, enable);
  output [7:0] y;
  input [7:0] a;
  input en;
  wire [7:0] y, a;
  wire en;
  
  //array of 8 Verilog tri-state primitives each bit of the
  //vectors is connected to a different primitive instance
  bufif1 u[7:0] (y, a, en);
endmodule

 

Syntax

 (drive_strength) #(delay)  [] (terminal,terminal, ... );

 #(delay)  [] (terminal, terminal, ... );

 

		Terminal Order
and or xor	nand nor xnor	(1_output, 1-or-more_inputs)
buf	not	(1-or-more_outputs, 1_input)
bufif0 bufif1	notif0 notif1	(1_output, 1_input, 1_control)
pullup	pulldown	(1_output)
		(1_output, 1-or-more_inputs)

 

		Terminal Order
pmos nmos	rpmos rnmos	(1_output, 1_input, 1_control)
cmos	rcmos	(1_output, 1_input, n_control, p_control)
tran	rtran	(2_bidirectional-inouts)
tranif0 rtranif0	rtranif1 rtranif1	(2_bidirectional-inouts, 1_control)

 

# or #()
   Single delay for all output transitions

#(, )
   Separate delays for (rising, falling) transitions

#(, , )
   Separate delays for (rising, falling, turn-off) transitions

#(::)
   Minimum to maximum range of delays for all transitions

#(::, ::)
   Min. to max. range of delays for (rising, falling) transitions

#(::, ::,::)
   Min. to max. range of delays for (rising, falling, turn-off) transitions

 

 (optional) represents the propagation delay through a primitive. The default delay is zero. Integers or real numbers may be used.

 (optional) is specified as (strength1, strength0) or (strength0, strength1) Refer to  for strength keywords.

Only gate primitives may have drive strength specified. Switch primitives pass the input strength to the output. Resistive switches reduce the strength as it passes through.

 (optional) may used to reference specific primitives in debugging tools, schematics, etc.

 (optional) instantiates multiple primitives, each instance connected to separate bits of a vector.

	The range is specified as [lhi:rhi] (left-hand-index to right-hand-index).
	The primitive instances are connected with the right-most instance index connected to the right-most bit of each vector, and progressing towards the left.
	Vector signals must be the same size as the array.
	Scalar signals are connected to all instances in the array.

 

Primitive Instance Examples	Notes
and i1 (out,in1,in2);	zero delay gate primitive
and #5 (o,i1,i2,i3,i4);	same delay for all transitions
not #(2,3) u7(out,in);	separate rise & fall delays
buf (pull0,strong1)(y,a);	output drive strengths model ECL
wire [31:0] y, a; buf #2.7 i[31:0] (y,a);	array of 32 buffers

 

Syntax

 @()
  : 
  
   

  

 

 is either initial or always

	initial procedural blocks process statements one time.
	always procedural blocks process statements repeatedly.

 (optional) is an event timing control that controls when all statements in the procedural block will start to be evaluated. The sensitivity list is used to model combinational and sequential logic behavior.

-- is used to group two or more procedural statements together and control the execution order.

	begin--end groups two or more statements together sequentially, so that statements are evaluated in the order they are listed. Each timing control is relative to the previous statement.
	fork--join groups two or more statements together in parallel, so that all statements are evaluated concurrently. Each timing control is absolute to when the group started.

 (optional) creates a local scope in a statement group. Named groups may have local variables, and may be disabled with the disablekeyword.

 (optional) must be a register data type (may only be declared in named statement groups).

 is used to control when statements in a procedural block are executed. Refer to Procedural Timing

 is a  to a register variable or a .

Procedural Block Examples	Notes
initial fork bus = 16'h0000; #10 bus = 16'hC5A5; #20 bus = 16'hFFAA; join	initial procedure executes statements one time; The fork--join group places statements in parallel.
always @(a or b or ci) begin sum = a + b + ci; end	always procedure executes statements repeatedly.
always @(posedge clk) q <= data;	a statement group is not required when there is only one statement

 

#delay

Delays execution for a specific amount of time. The delay may be a literal number, a variable, or an expression.

@(edge signal or edge signal or ... )

Delays execution until there is a logic transition on a signal.

	edge (optional) maybe either posedge or negedge. If no edge is specified, then any logic transition is used.
	or is used to specify events on any of several signals.
	signal may be scalar or vector, and any data type.

wait (expression)

Delays execution until the expression evaluates as true.

register_data_type = expression;

Blocking procedural assignment. Expression is evaluated and assigned when the statement is encountered. In a begin--end sequential statement group, execution of the next statement is blocked until the assignment is complete. In the sequence begin m=n; n=m; end, the 1st assignment changes m before the 2nd assignment evaluates m.

register_data_type <= expression;

Non-blocking procedural assignment. Expression is evaluated when the statement is encountered, and assignment is postponed until the end of the time-step. In a begin--end sequential statement group, execution of the next statement is not blocked; and may be evaluated before the assignment is complete. In the sequence begin m<=n; n<=m; end, both assignments will be evaluated before m or n changes.

 register_data_type = expression;
 register_data_type <= expression;

Delayed procedural assignments. Evaluation of the assignment is delayed by the timing control.

register_data_type =  expression;

Blocking intra-delayed assignment. Expression is evaluated in the time-step in which the statement is encountered, and assigned in a non-deterministic order in the time-step specified by the timing control.

register_data_type <=  expression;

Non-blocking intra-delayed assignment. Expression is evaluated in the time-step in which the statement is encountered, and assigned at the end of the time-step specified by the timing control. Models transport delay.

assign register_data_type = expression;

Procedural continuous assignment. Overrides any other procedural assignments to a register variable.

deassign register_data_type;

De-activates a procedural continuous assignment.

force net_or_register_data_type = expression;

Forces any data type to a value, overriding all other logic.

release net_or_register_data_type;

Removes the effect of a force.

if (expression)
   statement or statement_group

Executes the next statement or statement group if expression evaluates as true.

if (expression)
   statement or statement_group
else
   statement or statement_group

Executes the first statement or statement group if expression evaluates as true. Executes the second statement or statement group if expression evaluates as false or unknown.

case (net_or_register_or_literal)
   case_match1: statement or statement_group
   case_match2,
   case_match3: statement or statement_group
   default: statement or statement_group
endcase

Compares the net, register or literal value to each case and executes the statement or statement group associated with the first matching case. Executes the default if none of the cases match (a default case is optional).

casez (net_or_register_or_literal)

Special version of the case statement which uses a Z logic value to represent don't-care bits.

casex (net_or_register_or_literal)

Special version of the case statement which uses Z or X logic values to represent don't-care bits.

forever statement or statement_group

An infinite loop that continuously executes the statement or statement group.

repeat (number) statement or statement_group

A loop that executes the statement or statement group a set number of times. Number may be an integer, a variable, or an expression (a variable or expression is only evaluated when the loop is first entered).

while (expression) statement or statement_group

A loop that executes a statement or statement group as long as an expression evaluates as true.

for (initial_assignment; expression; step_assignment) statement or statement_group

	Executes initial_assignment once when the loop starts.
	Executes the statement or statement group as long as the expression evaluates as true.
	Executes the step_assignment at the end of each pass through the loop.

disable group_name;

Discontinues execution of a named group of statements. Simulation of that group jumps to the end of the group without executing any scheduled events.

Procedural Statement Examples

//A 50 ns clock oscillator that starts after 1000 time units
initial
  begin
    clk = 0;
    #1000 forever #25 clk = ~clk;
  end
    

//sensitivity list models sequential logic
always @(posedge clk)
  begin
    //Non-blocking assignments avoid race conditions in the byte swap
    word[15:8]<= word[7:0];
    word[7:0] <= word[15:8];
  end
    

//sensitivity list models combinational logic
always @(a or b or sel)
  if (sel==0) y = a + b;
  else y = a * b;
    

//sensitivity list models sequential logic
always @(posedge clk)
  begin
    casez (opcode) //casez makes Z a don't care
      //? in literal integer is same as Z
      2'b1??: alu_out = accum;
      2'b000: while (bloc_xfer) //loop until false
                repeat (5) @(posedge clk)
                  begin //loop 5 clock cycles
                    RAM[address] = data_bus;
                    address = address + 1;
                  end
      3'b011: begin : load //named group
                integer i; //local variable
                for (i=0; i<=255; i=i+1)
                  @(negedge clk)
                    data_bus = RAM[i];
              end
      default: $display("illegal opcode");
    endcase
  end