4096核的MIPS CPU

SAR architecture overviewThe TSAR shared memory architecture is a scalable, cache coherent,general-purpose multicore architecture. It is intended to supportcommodity applications and operating systems running on standard PCs,such as LINUX or FreeBSD. Therefore, the cache coherence must beentirely guaranteed by the hardware. Moreover, the TSAR architecturemust provide hardware support for a paginated virtual memory andefficient atomic operations for synchronization.
The main technical issue is the scalability, as this architecture isintended to integrate up to 4096 cores (even if the first prototypewill contain only 16 cores). The second technical issue is the powerconsumption, and all technical choices described below are driven bythese two goals......
还有MIT 的RAW().
同样是玩多核和MIPS,龙芯3与之比较一下，差距啊。