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分类: WINDOWS

2011-06-11 22:24:33

今天终于把ucosii使用GNUARM410编译通过,并通过vivi启动ucosii,能跑多任务了。。。

这几天主要是遇到ADS语法转GNU ARM汇编语法的问题,不过编译通过后,不代表能跑,我就卡在这里很久,很快就把几个汇编文件编译通过,加上ucos核心代码,使用GNUARM编译完成后,结果还是跑不起来,又不知道怎么入手调试,于是就利用开发板上的灯来指示,一步一步的调试,发现汇编文件没问题,结果就开始加入其他的文件,当加入任何一个C文件时,就出问题,老是连灯都不亮,证明没跑汇编文件,于是在产生的map文件中发现c函数名占用了0x30000000入口地址,那么就修改s3c2440.ld文件,把s3c2440/source/2440init.o指定在0x30000000入口地址位置,于是可以跑了,整个工程(包括ucos系统)也编译出来,然后跑,发现串口能打印数据,不过就是没跑动ucos多任务系统,搞了快一天,最后才发现,那个INT8U  const  OSUnMapTbl[256](os_core.c文件中)里的数据全部清0,立即就反应s3c2440.ld文件是不是把这初始化数据表给清空了,发现我把*(.rodata)放到了.data段,难怪被初始化为0了,于是放回到.text段中,结果正常跑通uosii多任务,找这个问题,弄的我调试汇编代码调了好久,各种方法都尝试过,发现任务优先级怎么老是0的,慢慢跟踪到os_core.c中的OSUnMapTabl表被清空了,一个字:累!

下面附Makefile, s3c2440.ld 和2440init.S文件内容:

(注:目前只是在Nor Flash上通过vivi启功ucosii系统的情况,没使用Nand Flash)

FILE: Makefile
===============================================================================
##################################################################
# @file: Makefile
# @author: NO.773 (xxx@xxx.com)
# history:
# @20110611: initial
#
##################################################################

# cygwin
CYG_GNU410_INC    = '/cygdrive/c/Program Files/GNUARM.410/lib/gcc/arm-elf/4.1.0'
CYG_GNU410_CLIB   = '/cygdrive/c/Program Files/GNUARM.410/arm-elf/lib'
CYG_GNU410_GCCLIB = '/cygdrive/c/Program Files/GNUARM.410/lib/gcc/arm-elf/4.1.0'
CYG_GNU410_BIN    = '/cygdrive/c/Program Files/GNUARM.410/bin'

DEL=rm

# vc6
GNU410_INC    = 'C:/Program Files/GNUARM.410/lib/gcc/arm-elf/4.1.0'
GNU410_CLIB   = 'C:/Program Files/GNUARM.410/arm-elf/lib'
GNU410_GCCLIB = 'C:/Program Files/GNUARM.410/lib/gcc/arm-elf/4.1.0'
GNU410_BIN    = 'C:/Program Files/GNUARM.410/bin'

# linux GCC 4.3.2
GNU432_INC    = '/usr/local/arm/4.3.2/arm-none-linux-gnueabi/libc/usr/include'
GNU432_CLIB   = '/usr/local/arm/4.3.2/arm-none-linux-gnueabi/libc/armv4t/usr/lib'
GNU432_GCCLIB = '/usr/local/arm/4.3.2/lib/gcc/arm-none-linux-gnueabi/4.3.2/armv4t'
GNU432_BIN    = '/usr/local/arm/4.3.2/bin'



ifdef COMSPEC
ifdef _VBOOT_VC6_
# vc6
ARM_INCLUDE   ?=$(GNU410_INC)
ARM_C_LPATH   ?=$(GNU410_CLIB)
ARM_GCC_LPATH ?=$(GNU410_GCCLIB)
ARM_BIN_PATH  ?=$(GNU410_BIN)
UCOSII_ROOT   ?=E:/SOLO_JOB/ucos_ii
else   
# cygwin
ARM_INCLUDE   ?=$(CYG_GNU410_INC)
ARM_C_LPATH   ?=$(CYG_GNU410_CLIB)
ARM_GCC_LPATH ?=$(CYG_GNU410_GCCLIB)
ARM_BIN_PATH  ?=$(CYG_GNU410_BIN)
UCOSII_ROOT   ?=$(shell /bin/pwd)
endif
else
# linux
ARM_INCLUDE   ?=$(GNU432_INC)
ARM_C_LPATH   ?=$(GNU432_CLIB)
ARM_GCC_LPATH ?=$(GNU432_GCCLIB)
ARM_BIN_PATH  ?=$(GNU432_BIN)
UCOSII_ROOT   ?=$(shell /bin/pwd)
endif

ifdef COMSPEC
#cygwin, vc6
CROSS_COMPILE = $(ARM_BIN_PATH)/arm-elf-
else
#linux
CROSS_COMPILE = $(ARM_BIN_PATH)/arm-linux-
endif

LINUX_INCLUDE_DIR = $(ARM_INCLUDE)

TOPDIR = $(VBOOT_ROOT)


ARCH = arm


AS              = $(CROSS_COMPILE)as
LD              = $(CROSS_COMPILE)ld
CC              = $(CROSS_COMPILE)gcc
CPP             = $(CC) -E
AR              = $(CROSS_COMPILE)ar
NM              = $(CROSS_COMPILE)nm
OBJCOPY         = $(CROSS_COMPILE)objcopy

SRC_UCOS = ucos_ii/source
SRC_ARM = ucos_ii/arm
SRC_API = ucos_ii/api
INC_ARCH = s3c2440/includes
SRC_ARCH = s3c2440/source
SRC_PRNT = printf

INCLUDES = \
-I$(SRC_UCOS) \
-I$(SRC_ARM) \
-I$(SRC_API) \
-I$(INC_ARCH) \
-I$(SRC_ARCH) \
-I$(SRC_PRNT) \

UCOS_SRCS = \
$(SRC_UCOS)/ucos_ii.c \
########################################
# ucos_ii.c had include below *.c files
########################################
#$(SRC_UCOS)/os_core.c \
#$(SRC_UCOS)/os_flag.c \
#$(SRC_UCOS)/os_mbox.c \
#$(SRC_UCOS)/os_mem.c \
#$(SRC_UCOS)/os_mutex.c \
#$(SRC_UCOS)/os_q.c \
#$(SRC_UCOS)/os_sem.c \
#$(SRC_UCOS)/os_task.c \
#$(SRC_UCOS)/os_time.c \
#$(SRC_UCOS)/os_tmr.c \
#$(SRC_UCOS)/os_dbg_r.c \

ARM_SRCS = \
$(SRC_ARM)/os_cpu_a.S \
$(SRC_ARM)/os_cpu_c.c \

ARCH_ARCS = \
$(SRC_ARCH)/2440init.S \
$(SRC_ARCH)/mmu.c \
$(SRC_ARCH)/2440slib.S \
$(SRC_ARCH)/nand.c \
$(SRC_ARCH)/2440lib.c \
$(SRC_ARCH)/main.c \
$(SRC_ARCH)/timer.c \
$(SRC_ARCH)/target.c \


PRNT_SRCS = \
$(SRC_PRNT)/printf.c \

OBJCOPYFLAGS = -R .comment -R .stab -R .stabstr

CLIBS = -L$(ARM_GCC_LPATH) -L$(ARM_C_LPATH)  -lc -lgcc

SOURCES =  $(UCOS_SRCS) $(ARM_SRCS) $(ARCH_ARCS) $(PRNT_SRCS)

OBJS := $(subst .c,.o,$(filter-out %.S,$(SOURCES)))
OBJS += $(subst .S,.o,$(filter-out %.c,$(SOURCES)))

all: ucosii

CFLAGS = $(INCLUDES) -Wall -Wstrict-prototypes -O2 -fPIC -fomit-frame-pointer
AFLAGS = $(CFLAGS)

LINKFLAGS = -Ts3c2440/s3c2440.lds -Bstatic


.PHONY: dummy

ucosii: $(OBJS) dummy
    $(LD) -v $(LINKFLAGS) $(OBJS) -o $@.elf $(CLIBS)
    $(NM) -v -l $@.elf > $@.map
    $(OBJCOPY) -O binary -S $@.elf $@.bin $(OBJCOPYFLAGS)

clean:
    $(DEL) -f $(OBJS)
    $(DEL) -f ucosii.bin ucosii.elf ucosii.map

##################################################
# common
##################################################
%.o: %.c
    $(CC) $< -c $(CFLAGS) -o $@
%.o: %.S
    $(CC) $< -c $(AFLAGS) -o $@

===============================================================================

FILE: s3c2440.ld
===============================================================================
ENTRY(_start)

SECTIONS {
    . = 0x30000000;
      .text : {s3c2440/source/2440init.o (.text); *(.rodata); *(.text) }
    Image_RO_Limit = .;   
    Image_RW_Base = .;
      .bss  ALIGN(4): { *(.bss) *(COMMON) }
    Image_RW_Limit = .;
    Image_ZI_Base = .;
      .data  ALIGN(4): { *(.data)}
    Image_ZI_Limit = .;   
    _end = .;
    end = .;
}
===============================================================================


FILE: 2440init.S
===============================================================================
#include "option.inc"
#include "memcfg.inc"
#include "2440addr.inc"

.extern Image_RO_Limit          @ End of ROM code (=start of ROM data)
.extern Image_RW_Base           @ Base of RAM to initialise
.extern Image_ZI_Base           @ Base and limit of area
.extern Image_ZI_Limit          @ to zero initialise

.extern    MMU_SetAsyncBusMode
.extern Main                    @ The main entry of mon program
.extern    CopyProgramFromNand
.extern OS_CPU_IRQ_ISR             @ uCOS_II IrqISR

.equ BIT_SELFREFRESH, (1<<22)

@ Pre-defined constants
.equ USERMODE,    0x10
.equ FIQMODE,    0x11
.equ IRQMODE,     0x12
.equ SVCMODE,     0x13
.equ ABORTMODE,    0x17
.equ UNDEFMODE,    0x1b
.equ MODEMASK,     0x1f
.equ NOINT,     0xc0

@ The location of stacks
.equ UserStack,    (_STACK_BASEADDRESS-0x3800)    @ 0x33ff4800 ~
.equ SVCStack,    (_STACK_BASEADDRESS-0x2800)    @ 0x33ff5800 ~
.equ UndefStack,(_STACK_BASEADDRESS-0x2400)    @ 0x33ff5c00 ~
.equ AbortStack,(_STACK_BASEADDRESS-0x2000)    @ 0x33ff6000 ~
.equ IRQStack,    (_STACK_BASEADDRESS-0x1000)    @ 0x33ff7000 ~
.equ FIQStack,    (_STACK_BASEADDRESS-0x0)    @ 0x33ff8000 ~

@ begin: Power Management
.equ Mode_USR,    0x10
.equ Mode_FIQ,    0x11
.equ Mode_IRQ,    0x12
.equ Mode_SVC,    0x13
.equ Mode_ABT,    0x17
.equ Mode_UND,    0x1B
.equ Mode_SYS,    0x1F

.equ I_Bit,        0x80
.equ F_Bit,        0x40

.if CONFIG==16
    .equ THUMBCODE, 1
    .code 32
.else
    .equ THUMBCODE, 0
.endif

.macro MOV_PC_LR
    .if THUMBCODE
        bx lr
    .else
        mov    pc, lr
     .endif
.endm
   
.macro MOVEQ_PC_LR
     .if THUMBCODE
           bxeq lr
     .else
        moveq pc, lr
    .endif
.endm
   
.macro HANDLER $HandleLabel
    sub        sp, sp, #4             @ decrement sp(to store jump address)
    stmfd    sp!, {r0}             @ PUSH the work register to stack(lr does''t push because it return to original address)
    ldr     r0, =\$HandleLabel     @ load the address of HandleXXX to r0
    ldr     r0, [r0]            @ load the contents(service routine start address) of HandleXXX
    str     r0, [sp,#4]           @ store the contents(ISR) of HandleXXX to stack
    ldmfd   sp!, {r0,pc}          @ POP the work register and pc(jump to ISR)
.endm


.text

.globl _start
_start:   
    b    ResetHandler
    b    HandlerUndef    @ handler for Undefined mode
    b    HandlerSWI        @ handler for SWI interrupt
    b    HandlerPabort    @ handler for PAbort
    b    HandlerDabort    @ handler for DAbort
    b    .                @ reserved
    b    HandlerIRQ        @ handler for IRQ interrupt
    b    HandlerFIQ        @ handler for FIQ interrupt
    @ 0x20
    b    EnterPWDN        @ Must be @0x20.

HandlerFIQ:        HANDLER HandleFIQ
HandlerIRQ:        HANDLER HandleIRQ
HandlerUndef:    HANDLER HandleUndef
HandlerSWI:        HANDLER HandleSWI
HandlerDabort:    HANDLER HandleDabort
HandlerPabort:    HANDLER HandlePabort


ResetHandler:   
    ldr    r0, =WTCON       @ watch dog disable
    ldr    r1, =0x0
    str    r1, [r0]

    ldr    r0, =CLKCON      @ com 1 disable
    ldr    r1, =0x1FFBF0
    str    r1, [r0]

    ldr    r0, =INTMSK
    ldr    r1, =0xffffffff  @ all interrupt disable
    str    r1, [r0]

    ldr    r0, =INTSUBMSK
    ldr    r1, =0x7fff         @ all sub interrupt disable
    str    r1, [r0]
   
#if 1   
    @ Led_Display
    ldr    r0,=GPBCON
    ldr    r1,=0x00155555
    str    r1,[r0]
    ldr r0, =GPBUP
    ldr r1,=0xff
    str r1,[r0]
    ldr    r0,=GPBDAT
    ldr    r1,=0x00
    str    r1,[r0]
#endif

    @ To reduce PLL lock time, adjust the LOCKTIME register.
    ldr    r0,=LOCKTIME
    ldr    r1,=0xffffff
    str    r1,[r0]

.if PLL_ON_START
    @ Setting value Fclk:Hclk:Pclk
    ldr    r0,=CLKDIVN
    ldr    r1,=CLKDIV_VAL        @ 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
    str    r1,[r0]
   
.if CLKDIV_VAL>1             @ means Fclk:Hclk is not 1:1.
    mrc p15,0,r0,c1,c0,0
    orr r0,r0,#0xc0000000     @ R1_nF:OR:R1_iA
    mcr p15,0,r0,c1,c0,0
.else
    mrc p15,0,r0,c1,c0,0
    bic r0,r0,#0xc0000000     @ R1_iA:OR:R1_nF
    mcr p15,0,r0,c1,c0,0
.endif

    @ Configure UPLL
    ldr    r0,=UPLLCON
    ldr    r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) 
    str    r1,[r0]
    nop    @ Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
    nop
    nop
    nop
    nop
    nop
    nop
    @ Configure MPLL
    ldr    r0,=MPLLCON
    ldr    r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)  @ Fin=12.0MHz
    str    r1,[r0]
.endif

    @ Check if the boot is caused by the wake-up from SLEEP mode.
    ldr    r1,=GSTATUS2
    ldr    r0,[r1]
    tst    r0,#0x2
    @ In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
    bne    WAKEUP_SLEEP
   
    .globl StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp:   
    @ Set memory control registers
     adr    r0,SMRDATA
    ldr    r1,=BWSCON        @ BWSCON Address
    add    r2, r0, #52        @ End address of SMRDATA
   
0:    ldr    r3, [r0], #4
    str    r3, [r1], #4
    cmp    r2, r0
    bne    0b

@ when EINT0 is pressed, clear SDRAM
@ check if EIN0 button is pressed
    ldr    r0,=GPFCON
    ldr    r1,=0x0
    str    r1,[r0]
    ldr    r0,=GPFUP
    ldr    r1,=0xff
    str    r1,[r0]

    ldr    r1,=GPFDAT
    ldr    r0,[r1]
    bic    r0,r0,#(0x1e<<1)  @ bit clear
    tst    r0,#0x1
    bne 1f
   
@ Clear SDRAM Start
    ldr    r0,=GPFCON
    ldr    r1,=0x55aa
    str    r1,[r0]
@    ldr    r0,=GPFUP
@    ldr    r1,=0xff
@    str    r1,[r0]
    ldr    r0,=GPFDAT
    ldr    r1,=0x0
    str    r1,[r0]

    mov r1,#0
    mov r2,#0
    mov r3,#0
    mov r4,#0
    mov r5,#0
    mov r6,#0
    mov r7,#0
    mov r8,#0
   
    ldr    r9,=0x4000000           @ 64MB
    ldr    r0,=0x30000000

0:    stmia    r0!,{r1-r8}
    subs    r9,r9,#32
    bne        0b

@ Clear SDRAM End

    @ Initialize stacks
1:    bl    InitStacks   

@ Check boot mode

    ldr    r0, =BWSCON
    ldr    r0, [r0]
    bic r0, r0, #0xfffffffc
    cmp    r0, #0                    @ OM[1:0] != 0, NOR FLash boot
    bne    on_the_ram                @ don not read nand flash

copy_myself:                    @ boot from nand flash
.if 1
    bl CopyProgramFromNand
.else
    mov    r5, #NFCONF
    ldr    r0, =(1<<12)|(4<<8)|(1<<4)|(0<<0)
    str    r0, [r5]
   
    ldr    r0,    =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
    str    r0, [r5,#0x04]
    bl    ReadNandID
    mov    r6, #0
    ldr    r0, =0xec73
    cmp    r5,    r0
    beq    1f
    ldr    r0, =0xec75
    cmp    r5, r0
    beq    1f
    mov    r6, #1
1:   
    bl    ReadNandStatus
   
    mov    r8, #0
    ldr    r9, =_start
2:   
    ands    r0, r8, #0x1f
    bne    3f
    mov    r0, r8
    bl    CheckBadBlk
    cmp    r0, #0
    addne    r8, r8, #32
    bne    4f
3:   
    mov    r0, r8
    mov    r1, r9
    bl    ReadNandPage
    add    r9, r9, #512
    add    r8, r8, #1
4:   
    cmp    r8, #5120             @ copy to sdram
    bcc    2b
   
    mov    r5, #NFCONF            @ DsNandFlash
    ldr    r0, [r5,#0x04]
    orr    r0, r0, #0x01
    str    r0, [r5,#0x04]
.endif   
    ldr    pc, =on_the_ram     @ jump to the sdram
   

on_the_ram:   
    @ Copy and paste RW data/zero initialized data
    ldr    r0, =Image_RO_Limit     @ Get pointer to ROM data
    ldr    r1, =Image_RW_Base      @ and RAM copy
    ldr    r3, =Image_ZI_Base

    @ Zero init base => top of initialised data
    cmp    r0, r1              @ Check that they are different
    beq    2f

1:    cmp        r1, r3          @ Copy init data
    ldrcc    r2, [r0], #4    @ --> LDRCC r2, [r0] + ADD r0, r0, #4
    strcc    r2, [r1], #4    @ --> STRCC r2, [r1] + ADD r1, r1, #4
    bcc        1b

2:    ldr    r1, =Image_ZI_Limit @ Top of zero init segment
    mov    r2, #0

3:    cmp        r3, r1              @ Zero init
    strcc    r2, [r3], #4
    bcc        3b

      @ Setup IRQ handler
    ldr    r0,=HandleIRQ       @ This routine is needed
    @ldr r1,=IsrIRQ              @ if there is not 'subs pc,lr,#4' at 0x18, 0x1c
    ldr    r1, =OS_CPU_IRQ_ISR @ modify by txf, for ucos
    str    r1,[r0]

.if THUMBCODE<>1
    bl    Main        @ Don NOT use main() because ...
    b    .
.endif

.if THUMBCODE         @ for start-up code for Thumb mode
    orr    lr,pc,#1
    bx    lr
    .code 16
    bl    Main        @ Do not use main() because ......
    b    .
    .code 32
.endif

@ function initializing stacks
InitStacks:   
    @ Do not use DRAM,such as stmfd,ldmfd......
    @ SVCstack is initialized before
    @ Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
    mrs    r0,cpsr
    bic    r0,r0,#MODEMASK
    orr    r1,r0,#UNDEFMODE|NOINT
    msr    cpsr_cxsf,r1        @ UndefMode
    ldr    sp,=UndefStack        @ UndefStack=0x33FF_5C00

    orr    r1,r0,#ABORTMODE|NOINT
    msr    cpsr_cxsf,r1        @ AbortMode
    ldr    sp,=AbortStack        @ AbortStack=0x33FF_6000

    orr    r1,r0,#IRQMODE|NOINT
    msr    cpsr_cxsf,r1        @ IRQMode
    ldr    sp,=IRQStack        @ IRQStack=0x33FF_7000

    orr    r1,r0,#FIQMODE|NOINT
    msr    cpsr_cxsf,r1        @ FIQMode
    ldr    sp,=FIQStack        @ FIQStack=0x33FF_8000

    bic    r0,r0,#MODEMASK|NOINT
    orr    r1,r0,#SVCMODE
    msr    cpsr_cxsf,r1        @ SVCMode
    ldr    sp,=SVCStack        @ SVCStack=0x33FF_5800

    @ USER mode has not be initialized.

    mov    pc,lr
    @ The LR register will not be valid if the current mode is not SVC mode.



@ void EnterPWDN(int CLKCON);
EnterPWDN:   
    mov r2,r0        @r2=rCLKCON
    tst r0,#0x8        @SLEEP mode?
    bne ENTER_SLEEP

ENTER_STOP:   
    ldr r0,=REFRESH
    ldr r3,[r0]        @r3=rREFRESH
    mov r1, r3
    orr r1, r1, #BIT_SELFREFRESH
    str r1, [r0] @ Enable SDRAM self-refresh

    mov r1,#16 @ wait until self-refresh is issued. may not be needed.
0:    subs r1,r1,#1
    bne 0b

    ldr r0,=CLKCON        @enter STOP mode.
    str r2,[r0]

    mov r1,#32
0:    subs r1,r1,#1    @1) wait until the STOP mode is in effect.
    bne 0b        @2) Or wait here until the CPU&Peripherals will be turned-off
   
    @ Entering SLEEP mode, only the reset by wake-up is available.
    ldr r0,=REFRESH @exit from SDRAM self refresh mode.
    str r3,[r0]
    MOV_PC_LR

ENTER_SLEEP:   
    @NOTE.
    @1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
    ldr r0,=REFRESH
    ldr r1,[r0]        @r1=rREFRESH
    orr r1, r1, #BIT_SELFREFRESH
    str r1, [r0]        @Enable SDRAM self-refresh

    mov r1,#16 @Wait until self-refresh is issued,which may not be needed.
0:    subs r1,r1,#1
    bne 0b

    ldr    r1,=MISCCR
    ldr    r0,[r1]
    orr    r0,r0,#(7<<17)  @Set SCLK0=0, SCLK1=0, SCKE=0.
    str    r0,[r1]

    ldr     r0,=CLKCON        @ Enter sleep mode
    str     r2,[r0]

    b     .            @CPU will die here.


WAKEUP_SLEEP:   
    @Release SCLKn after wake-up from the SLEEP mode.
    ldr    r1,=MISCCR
    ldr    r0,[r1]
    bic    r0,r0,#(7<<17)  @SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
    str    r0,[r1]

    @Set memory control registers
     ldr    r0,=SMRDATA    @be careful!
    ldr    r1,=BWSCON    @BWSCON Address
    add    r2, r0, #52    @End address of SMRDATA
0:   
    ldr    r3, [r0], #4
    str    r3, [r1], #4
    cmp    r2, r0
    bne    0b

    mov r1,#256
0:    subs r1,r1,#1    @1) wait until the SelfRefresh is released.
    bne 0b

    ldr r1,=GSTATUS3     @GSTATUS3 has the start address just after SLEEP wake-up
    ldr r0,[r1]

    mov pc,r0



.align 4

@ _ISR_STARTADDRESS=0x33FF_FF00
.equ HandleReset,        (_ISR_STARTADDRESS+4*0)
.equ HandleUndef,        (_ISR_STARTADDRESS+4*1)
.equ HandleSWI,            (_ISR_STARTADDRESS+4*2)
.equ HandlePabort,        (_ISR_STARTADDRESS+4*3)
.equ HandleDabort,        (_ISR_STARTADDRESS+4*4)
.equ HandleReserved,    (_ISR_STARTADDRESS+4*5)
.equ HandleIRQ,            (_ISR_STARTADDRESS+4*6)
.equ HandleFIQ,            (_ISR_STARTADDRESS+4*7)
@ 0x33FF_FF20  -- IntVectorTable
    .globl HandleEINT0    @ for os_cpu_a.s
.equ HandleEINT0,        (_ISR_STARTADDRESS+4*8)
.equ HandleEINT1,        (_ISR_STARTADDRESS+4*9)
.equ HandleEINT2,        (_ISR_STARTADDRESS+4*10)
.equ HandleEINT3,        (_ISR_STARTADDRESS+4*11)
.equ HandleEINT4,        (_ISR_STARTADDRESS+4*12)
.equ HandleEINT8,        (_ISR_STARTADDRESS+4*13)
.equ HandleCAM,            (_ISR_STARTADDRESS+4*14)
.equ HandleBATFLT,        (_ISR_STARTADDRESS+4*15)
.equ HandleTICK,        (_ISR_STARTADDRESS+4*16)
.equ HandleWDT,            (_ISR_STARTADDRESS+4*17)
.equ HandleTIMER0,        (_ISR_STARTADDRESS+4*18)
.equ HandleTIMER1,        (_ISR_STARTADDRESS+4*19)
.equ HandleTIMER2,        (_ISR_STARTADDRESS+4*20)
.equ HandleTIMER3,        (_ISR_STARTADDRESS+4*21)
.equ HandleTIMER4,        (_ISR_STARTADDRESS+4*22)
.equ HandleUART2,        (_ISR_STARTADDRESS+4*23)
.equ HandleLCD,            (_ISR_STARTADDRESS+4*24)
.equ HandleDMA0,        (_ISR_STARTADDRESS+4*25)
.equ HandleDMA1,        (_ISR_STARTADDRESS+4*26)
.equ HandleDMA2,        (_ISR_STARTADDRESS+4*27)
.equ HandleDMA3,        (_ISR_STARTADDRESS+4*28)
.equ HandleMMC,            (_ISR_STARTADDRESS+4*29)
.equ HandleSPI0,        (_ISR_STARTADDRESS+4*30)
.equ HandleUART1,        (_ISR_STARTADDRESS+4*31)
.equ HandleNFCON,        (_ISR_STARTADDRESS+4*32)
.equ HandleUSBD,        (_ISR_STARTADDRESS+4*33)
.equ HandleUSBH,        (_ISR_STARTADDRESS+4*34)
.equ HandleIIC,            (_ISR_STARTADDRESS+4*35)
.equ HandleUART0,        (_ISR_STARTADDRESS+4*36)
.equ HandleSPI1,        (_ISR_STARTADDRESS+4*37)
.equ HandleRTC,            (_ISR_STARTADDRESS+4*38)
.equ HandleADC,            (_ISR_STARTADDRESS+4*39)
@ 0x33FF_FFA0


.align 4
SMRDATA:
    .long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   @GCS0
    .long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   @GCS1
    .long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   @GCS2
    .long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   @GCS3
    .long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   @GCS4
    .long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   @GCS5
    .long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))                                                          @GCS6
    .long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))                                                          @GCS7
    .long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
    .long 0x32        @SCLK power saving mode, BANKSIZE 128M/128M
    .long 0x30        @MRSR6 CL=3clk
    .long 0x30        @MRSR7 CL=3clk

===============================================================================
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