MMU Initial In ViVi

project     :  MMU Initial In ViVi
instruction :  (None)

--  _________________________________0x3400_0000 ( total: 64 M )
--  |  ViVi (1M)                |
--  |___________________________|____0x33F0_0000 ( ViViRAM_BASE)
--  |  Heap (1M)                |
--  |___________________________|____0x33E0_0000 ( Heap_BASE )
--  |  MMU Table (16K)          |
--  |___________________________|____0x33DF_C000 ( MMU_Table_BASE )
--  |  Priviate Data(16K x 3)   |
--  |___________________________|____0x33DF_0000 ( ViVi_Priv_RAM_BASE )
--  |  Stack (32K)              | 
--  |___________________________|____0x33DE_8000 ( STACK_BASE )
--  |                           |
--  |  61.90625 (M)             |
--  |                           |
--  |___________________________|____0x3000_0000 ( RAM_BASE )


MMU Table Initial Chart:

--  |___________________________|____0x33E0_0000 ( Heap_BASE )
--  |  MMU Table (16K)          |
--  |       ... ...             |
--  |       ... ...             |
--  |___________________________|____0x33DF_C368
--  | 64 | MMU_SECDESC          |
--  |___________________________|____0x33DF_C364
--  |63|MMU_SECDESC|MMU_CACHEABLE|
--  |___________________________|____0x33DF_C363
--  |        ... ...            |
--  |        ... ...            |
--  |___________________________|____0x33DF_C303
--  |1|MMU_SECDESC|MMU_CACHEABLE|
--  |___________________________|____0x33DF_C302
--  |0|MMU_SECDESC|MMU_CACHEABLE|
--  |___________________________|____0x33DF_C301
--  |        ... ...            |
--  |        ... ...            |
--  |___________________________|____0x33DF_C008
--  | 1 | MMU_SECDESC           |
--  |___________________________|____0x33DF_C004
--  | 0 | MMU_SECDESC           |
--  |___________________________|____0x33DF_C000 ( MMU_Table_BASE )

-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
code :
static inline void mem_mapping_linear(void)
{
    unsigned long pageoffset, sectionNumber;
    putstr_hex("MMU table base address = 0x", (unsigned long)mmu_tlb_base);
    for (sectionNumber = 0; sectionNumber < 4096; sectionNumber++) {
        pageoffset = (sectionNumber << 20);
        *(mmu_tlb_base + (pageoffset >> 20)) = pageoffset | MMU_SECDESC;
    }

    /* make dram cacheable */
    for (pageoffset = DRAM_BASE; pageoffset < (DRAM_BASE+DRAM_SIZE); pageoffset += SZ_1M) {
        //DPRINTK(3, "Make DRAM section cacheable: 0x%08lx\n", pageoffset);
        *(mmu_tlb_base + (pageoffset >> 20)) = pageoffset | MMU_SECDESC | MMU_CACHEABLE;
    }
}
-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+