module state_machine(
clk, //48M
reset, //
sel, //01
Q //01
);
input clk; //
input reset; //
input sel;
output [3:0] Q; //
reg [3:0] Q; //
wire clk_out; //1S
reg [2:0] sts;
parameter st1 = 2'b00, //1
st2 = 2'b01, //2
st3 = 2'b10, //3
st4 = 2'b11; //4
/* */
always @(posedge clk_out or negedge reset)
begin
if(!reset)
begin
Q <= 4'b0000; //0
sts <= st1;
end
else
case(sts)
st1: //1
begin
Q <= 4'b1110; //0
if(sel) sts <= st2; //sel
else sts <= st4;
end
st2: //2
begin
Q <= 4'b1101; //
if(sel) sts <= st3; //sel
else sts <= st1;
end
st3: //3
begin
Q <= 4'b1011; //
if(sel) sts <= st4; //sel
else sts <= st2;
end
st4: //4
begin
Q <= 4'b0111; //
if(sel) sts <= st1; //sel
else sts <= st3;
end
default:sts <= st1; //0
endcase
end
clk_div clk_div_0( //2S
.clk(clk), //48M
.reset(reset), //
.clk_out(clk_out) //
);
endmodule
module clk_div
(
clk, //时钟输入,48M
reset, //异步复位输入,高电平复位
clk_out //分频时钟输出
);
parameter cnt_top=26'd12000000; //分频系数
input clk; //端口定义
input reset;
output clk_out;
reg clk_out; //寄存器定义
reg [25:0] clk_cnt;
always @(posedge clk or negedge reset)
begin
if(!reset) //复位
begin
clk_out <= 1'b0;
clk_cnt <= 0;
end
else
begin
if(clk_cnt==cnt_top-1)
begin
clk_out <= ~clk_out; //分频输出
clk_cnt <= 0;
end
else
clk_cnt <= clk_cnt+1'b1; //计数器加1
end
end
endmodule
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