--一个全加器
entity Full_Adder is
generic (TS : TIME :=0.11 ns; TC : TIME :=0.1 ns);
port (X,Y,Cin: in BIT; Cout,Sum: out BIT);
end Full_Adder;
architecture Behave of Full_Adder is
begin
Sum <= X xor Y xor Cin after TS;
Count <= (X and Y)or(X and Cin)or(Y and Cin) after TC;
end;
--一个8位行波进位加法器
entity Adder8 is
port(A,B: in BIT_VECTOR(7 downto 0);
Cin: in BIT; Cout: out BIT;
Sum: out BIT_VECTOR(7 downto 0));
end Adder8;
architecture Structure of Adder8 is
component Full_Adder
port (X,Y,Cin: in BIT; Cout,Sum: out BIT);
end component;
signal C: BIT_VECTOR(7 downto 0);
begin
Stages: for i in 7 downto 0 generate
LowBit: if i=0 generate
FA: Full_Adder port map(A(0),B(0),Cin,C(0),Sum(0));
end generate;
OtherBits: if i /=0 generate
FA: Full_Adder port map(A(i),B(i),C(i-1),C(i),Sum(i));
end generate;
Cout <= C(7);
end;
--上升沿触发的异步清零的D触发器
entity DFFClr is
generic (TRQ : TIME :=2 ns; TCQ : TIME :=2 ns);
port(CLR,CLK,D: in BIT;Q,QB: out BIT);
end;
architecture Behave of DFFClr is
signal Qi: BIT;
begin
QB <= not Qi; Q <= Qi;
process(CLR,CLK)
begin
if CLR='1' then Qi <= '0' after TRQ;
elsif CLK'EVENT and CLK='1' then
Qi <= D after TCQ;
end if;
end process;
end;
--一个8位寄存器
entity Register8 is
port(D: in BIT_VECTOR(7 downto 0);
Clk,Clr: in BIT;
Q: out BIT_VECTOR(7 downto 0));
end;
architecture Structure of Register8 is
component DFFClr
port(CLR,CLK,D: in BIT;Q,QB: out BIT);
end component;
begin
Stages: for i in 7 downto 0 generate
FF: DFFClr port map (Clr,Clk,D(i),Q(i),open);
end generate;
end;
--8位多路选择器
entity Mux8 is
generic (TPD : TIME :=1 ns);
port(A,B: in BIT_VECTOR(7 downto 0);
Sel : in BIT :='0';
Y: out BIT_VECTOR(7 downto 0));
end;
architecture Behave of Mux8 is
begin
Y <= A after TPD when Sel ='1' else B after TPD;
end;
--一个零检测器
entity AllZero is
generic (TPD :TIME := 1ns);
port(X: in BIT_VECTOR; F : out BIT);
end;
architecture Behave of AllZreo is
begin
process(X)
begin
F<='1' after TPD;
for j in X'range loop
if X(j) = '1' then F <= '0' after TPD; end if;
end loop;
end process;
end;
--可变宽度移位寄存器
entity ShiftN is
generic (TCQ :TIME := 0.3 ns; TLQ :TIME := 0.5 ns; TSQ :TIME := 0.7ns);
port(CLK,CLR,LD,SH,DIR: in BIT;
D: in BIT_VECTOR;
Q: out BIT_VECTOR);
begin assert (D'LENGTH <= Q'LENGTH)
report "D wider than output Q" severity Failure;
end ShiftN;
architecture Behave of ShiftN is
begin
Shift: process(CLR,CLK)
subtype InB is NATURAL range D'LENGTH-1 downto 0;
subtype OutB is NATURAL range Q'LENGTH-1 downto 0;
variable St: BIT_VECTOR(OutB);
begin
if CLR='1' then
St := (others => '0'); Q <= St after TCQ;
elsif CLK'EVENT and CLK='1' then
if LD = '1' then
St := (others => '0');
St(InB) := D;
Q <= St after TLQ;
elsif SH='1' then
case DIR is
when '0' => St := '0' & St(St'LEFT downto 1);
when '1' => St := St(St'LEFT-1 downto 0) & '0';
end case;
Q <= St after TSQ;
end if;
end if;
end process;
end;
--状态机
--对两个二进制数A和B的乘法，我们可以用下面的算法
--1、如果A的LSB为'1'，则把把B加到累加器中
--2、A右移一位，B左移一位
--3、当A所有位为零时停止
--Moore有限状态机(输出只取决于状态)乘法器的VHDL模型
entity SM_1 is
generic(TPD :TIME := 1ns);
port(Start,Clk,LSB,Stop,Reset:in BIT;
Init,Shift,Add,Done :out BIT);
end;
architecture Moore of SM_1 is
type STATETYPE is (I,C,A,S,E);
signal State: STATETYPE;
begin
Init <= '1' after TPD when State = I else '0' after TPD;
Add <= '1' after TPD when State = A else '0' after TPD;
Shift<= '1' after TPD when State = S else '0' after TPD;
Done <= '1' after TPD when State = E else '0' after TPD;
process(CLK,Reset)
begin
if Reset = '1' then State <= E;
elsif CLK'EVENT and CLK='1' then
case State is
when I => State <= C;
when C =>
if LSB='1' then State <= A;
elsif Stop = '0' then State <= S;
else State <= E;
end if;
when A => State <= S;
when S => State <= C;
when E =>
if Start = '1' then State <= I; end if;
end case;
end if;
end process;
end;
--乘法器
entity Mult8 is
port(A,B: in BIT_VECTOR(3 downto 0);
Start,CLK,Reset: in BIT;
Result: out BIT_VECTOR(7 downto 0);
Done:out BIT);
end Mult8;
architecture Structure of Mult8 is use work.Mult_Components.all;
signal SRAA,SRBB,ADDout,MUXout,REGout: BIT_VECTOR(7 downto 0);
signal Zero,Init,Shift,Add,Low: BIT :='0';
signal High: BIT :='1';
signal F,OFL,REGclr: BIT;
begin
REGclr <= Init or Reset;
Result <= REGout;
SR1: ShiftN port map(clk=>clk,clr=>reset,ld=>init,sh=>shift,dir=>low,d=>a,Q=>sraa);
SR2: ShiftN port map(clk=>clk,clr=>reset,ld=>init,sh=>shift,dir=>high,d=>b,q=>srbb);
Z1 : AllZero port map(x=>sraa,f=>zero);
A1 : Adder8 port map(a=>srbb,b=>regout,cin=>low,cout=>OFL,sum<=addout);
M1 : Mux8 port map(A=>ADDout,b=>regout,sel=>add,y=>muxout);
R1 : Register8 port map(D=>muxout,q=>REGout,clk=clk,clr=>REGclr);
F1 : SM_1 port map(Start,clk,SRAA(0),Zero,Reset,Init,Shift,Add,Done);
end;
