Using PCI 9656 data receive card design

[abstract]PCI 9656 are PLX corporate design section of high speed PCI the I/O chip, may apply in 66MHz, 64bit PCI and the CompactPCI main line. The article has summarized the PCI 9656 major functions, introduced one kind applies PCI 9656 CompactPCI data receive card design. In the design used MAXII series CPLD to establish PCI 9656 with the FIFO data channel, might satisfy the high speed data transmission the request. 
[key words]PCI 9656; CompactPCI; Data receive card

[Abstract]The PCI 9656, a high-speed I/O accelerator of PLX Technology, Inc, supports 66MHz, 64bit PCI (and CompactPCI) bus operation. This paper describes its main functions and introduces a design of data-receiving card with PCI 9656, based on CompactPCI bus. A bridge is set up with MAXII CPLD between PCI 9656 and FIFO interface, providing the high-speed data-receiving capability.

[Key words]PCI 9656; CompactPCI; data-receiving card

 

The data transmission is in the digital signal processing process important link, its efficiency influence entire data processing system’s performance. The data transmission often uses in the profession the standardized bussing technique, makes number system’s design reliable, convenient, easy to promote. PCI takes one kind of mature main line standard, applies in many system’s data transmission processes. Unified the PCI electrical specification and the fine physical characteristics in view of the industry environment establishment’s CompactPCI standard, is more widespread in industrial field’s application. When design based on PCI or CompactPCI main line’s digital equipment, uses general PCI which various companies provide I/O chip or IP nucleus, may simplify the complex PCI connection design, speeds up the product the research and development and the promotion. PCI 9656 are PLX Corporation the general I/O chip which (CompactPCI) the main line application designs for high speed PCI, is suitable in 66MHz, 64bit PCI (CompactPCI) the main line, has provided 528MB/s (the PCI main line) and 264MB/s (local bus) the burst transmission speed, can satisfy the mostly high speed figure system’s performance requirement.

1 PCI 9656 function summaries

PCI 9656 support 66MHz, 64bit PCI the R2.2 standard, has provided compatible PICMG 2.1 R2.0 standard CompactPCI Hot the Swap connection, its local bus achieves 66MHz, 32bit (to support 0~66MHz, 8/16bit), but is PCI (CompactPCI) the adapter and the embedded system design provides the high performance the bus interface. The PCI 9656 disposition registers and PCI 9054, PCI9056 are compatible, also has facilitated the original design transplant.

PCI 9656 have 6 independent data channels, uses in Direct Master, Direct Slave as well as under the DMA functioning pattern data transmission, its deep FIFO designed has promoted main line’s burst transmission performance effectively.

1 Direct Master pattern. Uses in the local bus to PCI (CompactPCI) data transmission, 16 QWords (128byte) and 32 QWords (256byte) FIFO applies respectively in the data reads, writes the channel.

2 Direct Slave pattern. Uses in PCI (CompactPCI) to local bus’s data transmission, 16 QWords (128byte) and 32 QWords (256byte) FIFO applies respectively in the data reads, writes the channel.

3 DMA patterns. PCI 9656 have provided two DMA channels (Channel 0, Channel 1), has used two independent 32 QWords (256byte) bidirectional FIFO. Two DMA channels may simultaneously transmit the data, registers may dispose its priority relations through PCI 9656 MARBR. PCI 9656 DMA ways have the conventional block pattern (Block mode) and the collection and distribution pattern (Scatter/Gather mode), moreover supports by DREQ#, the DASK# signal request, the reply order pattern (Demand mode), may apply in the correspondence domain the real time data transmission.

In the partial total terminal, PCI 9656 simplified the data transmission control logic, was similar with the ISA main line, facilitates the transmission control design to realize. The PCI 9656 local buses have three kind of application patterns, may be suitable the different embedded processor.

1 M pattern. Supports Motorola 32bit the processor, provided has been possible with MPC850, MPC860 the PowerQCICC direct connected connection.

2 C patterns. Suits the majority processor’s general patterns, uses this pattern in the design.

3 J patterns. Is similar with the C pattern, but its address wire and data line multiplying.

2 data receive card design

The PCI 9656 internal fruitful in resources, the function is diverse, uses PCI 9656 is the connection chip, but carries on PCI conveniently (Compact) adapter’s design. But in the PCI 9656 part total terminals, often does not need to realize its complete logical function, may rest on needs to select the disposition, the further simplification design.

Figure 1 is applies PCI 9656 CompactPCI data name plate the design diagram, this data receive card applies in a section of synthetic aperture radar’s data recorder, the data pool is the 34bit difference signal, the 32bit data, the 1bit sampling clock, the 1bit data effective flag bit. In Figure 1: The clock actuates ICS553 to the PCI 9656, logical control module and FIFO provides the synchronized clock signal; The initialization disposition chip uses Microchip the 93LC56B, PCI 9000 series to provide 3 E2PROM serial interfaces, may when the system the electricity initialization internal disposition register; And 390 completes the difference to the single end signal’s transformation by way of Ti Corporation’s LVDT386; FIFO has used high speed, low power loss 72T36135M which IDT Corporation designs, the data capacity for 512K×36bit, use easy cascade First Word Follow Through working pattern; The logical control part uses Altera MAXII EPM1270, realizes data transmission controls FIFO to the PCI 9656 local bus’s between.

2.1 PCI9656 design applications

In the CompactPCI end, PCI 9656 provided 66MHz, the 64bit main line application to need the signal, might rest on the CompactPCI standard connection, through the simple exterior electric circuit, might realize Hot the Swap function.

In the partial total terminal, has used PCI 9656 C patterns. Under the C pattern, the PCI 9656 local buses may dispose realize three kind of data transmission logic. (1) Single cycle mode. Each time transmits 1 data (8/16/32bit), default mode of transmission. (2) Burst-4 mode. Each time 4 data, apply Intel i960 and IBM time the PPC401 processor’s recommendation pattern. (3) Continuous burst mode. The multi-data the burst transmission pattern, has provided the biggest data volume of goods handled continuously. In the transmission process, from the equipment (Slave) may through the Bterm# signal stop transmission process. The pattern 2 elect with pattern 3 its one, pattern 1 throughout available. In the data receive card, used has arisen suddenly (Continuous burst) continuously the pattern, might the effective use local bus band width.

Analysis receive card design: The partial total terminal does not have the processor, PCI 9656 in this end primarily equipment (Master), takes the main line throughout, is responsible for the logical control CPLD is from the equipment (Slave), responds PCI throughout 9656. The data transmission process has only used PCI 9656 Direct Slave and the DMA pattern, moreover does not need DMA the order pattern, in the movement process the data through the FIFO unidirectional transmission, cannot decode the address signal, the control may through write the order code to CPLD to complete. Therefore, may to PCI 9656 many signal simplification processing, only probably realize the following signal succession request:

LD[31:0],32bits data signal.

ADS#, the main line operates start symbol.

Blast#, burst transmission end mark.

LW/R#, writes/reads the signal.

Wait#, the main equipment suspends the transmission signal, the signal symbolized invalid the main equipment is normal.

Ready#, completes the signal from the equipment operation, the signal effective symbol is normal from the equipment.

EOT#, the data transmission exceptionally stops the signal, uses in the FIFO overflow or the free time interrupt data transmission.

Lint#, the signal of stop input, uses in causing the CompactPCI total terminal interrupt.

LRST#, partial total terminal reset.

Signal after simplification, in the normal read-write operation, only needs to process ADS#, Blast#, LW/R#, Wait#, Ready# and the data logical relation, Single cycle may think that is the Continuous burst exceptional case, thus two kind of pattern under logical succession unification processing. In the normal operation, ADS#, Blast#, Wait#, Ready# need satisfied logical relation as shown in Figure 2:

In Figure 2, ADS#, Blast#, the Wait# signal by the PCI 9656 actuations, LW/R# (in Figure 2 has not sectioned out) also by the PCI 9656 actuations, is in the entire process low or high, symbolized that the PCI 9656 pair of main lines read or write the operation. Ready# actuates by CPLD, Data is the bidirectional signal. When CPLD idling condition monitors the ADS# signal, once ADS# is effective, changes over to according to LW/R# reads or writes the operation. Reads in the operation, CPLD the FIFO data read-out, simultaneously sets at Ready# for the effective condition, must monitor when Wait#, Wait# is invalid, only then may continue the read next data; Writes in the operation, CPLD must set Ready# for the effective condition, monitors when Wait#, Wait# is invalid, CPLD only then may complete on the main line data read-in; When CPLD examines Blast#, Wait#, Ready# is the effective condition, then completes the last data the transmission operation, transfers to the idling condition.

Realizes the above data transmission logic, in addition the suitable unusual circumstance and the test switching control, then may design CPLD the logical control module.

2.2 MAXII EPM1270 application

The MAXII series is Altera Corporation’s new construction CPLD, compares with traditional construction’s CPLD, the MAXII power loss and the cost reduce largely, the resources density and the performance actually obviously promote, is suitable for the connection between the controlling agreement transformation. In the design has used MAXII EPM1270 model CPLD, its design structure as shown in Figure 3. MAXII the EPM1270 interior mainly divides into the logical control, the test, the FIFO three modules:

1 FIFO uses the IP nucleus which Altera provides to realize, the capacity may act according to the resources use situation adjustment, uses FWFT (First Word Follow Through) the pattern, is CPLD provides with the exterior FIFO simple connection.

2 test modules have the test data, the control data channel cut between the real data pool and the test data pool, when test receive card uses.

in 3 logical control module has exceptionally with the test control, the phase transition controls two parts, carries on the correspondence through a 8bit register. (1) the register controls CPLD the test module, the condition choice, simultaneously records FIFO the change of state. (2) exceptionally with the test control section basis condition register content control test module, monitors FIFO the overflow, half-full, spatial and so on conditions, produces the Lint# signal or through controls the register to transmit the phase transition control section, causes it effective EOT#, interrupts the data transmission. (3) phase transition control section execution local bus’s data read-write logic, has established four conditions: S0, idling condition; S1, the data reads the condition; S2, the register reads the condition; S3, the order writes the condition. Under the S0 condition acts according to the LW/R# signal and the register content determination to S1, S2, the S3 condition transformation. Under the S1 condition reads the FIFO data, produces according to the FIFO condition exceptionally stops signal EOT#. Under the S2 condition reads the 8bit register content. Under the S3 condition reads in the order code to the 8bit register to rewrite and reset its related bit position, thus controls CPLD the test module, cuts S1, the S2 condition, clear spatial FIFO.

Through the above design module, MAXII CPLD then may 9656 establish a simple and direct data-transmission channel in PCI with IDT 72T36135M between.

3 concluding remark

PCI 9656 have used the PLX Corporation field leading data channel construction technology, its rich function (CompactPCI) the main line application has provided the simple and direct I/O design way for high speed PCI. The article introduced uses PCI 9656 design section to apply as PCI a I/O in 66Mhz, 64bit the CompactPCI bus system’s data receive card. This article author innovates the spot: 1 9656 applies PCI in 66Mhz, 64bit the CompactPCI bus system, satisfies the high speed data transmission the request. 2 use in CPLD to construct FIFO the IP nucleus to realize FIFO and the PCI 9656 connection connections, optimized the CPLD transformation logic.

 

Reference:

[1] PLX Technology, Inc, PCI 9656BA Data Book Version1.1,2003.10.

[2] Altera Corporation, MAX II Device Handbook,2005.8.

[3] Integrated Device Technology, Inc, IDT72T36135M Data Sheet,2005.9.

[4] the Shen feather, Qi Weimin, opens resolute, real-time high speed data gathering and memory system’s one kind realizes the method, micro computer information, 2006,1-1:83-85.