通过cp15协处理器flush dcache总线上的数据回DDR和SRAM
文章来源：http://gliethttp.cublog.cn
//gliethttp_20080318
以下dcahe回写代码摘自linux2.6.24内核arm930处理器的(Tavor)
/arch/arm/mm/proc-xsc3.S目录
实现：短暂的禁用dcache和MMU,所以bl flush_i_d_cache之后需要再打开一次MMU
;//gliethttp_20080318 add icache dcache off and both on function
ALIGN 4
EXPORT flush_i_d_cache
flush_i_d_cache
stmfd {r0,lr}
mov r0, #0x1f00
orr r0, r0, #0x00e0
1 mcr p15, 0, r0, c7, c14, 2 @ clean/invalidate L1 D line
adds r0, r0, #0x40000000
bcc 1b
subs r0, r0, #0x20
bpl 1b
mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
mcr p15, 0, ip, c7, c10, 4 @ data write barrier
mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
;mcr p15, 0, r0, c7, c6, 0
ldmfd {r0,pc}
ALIGN 4
EXPORT disable_i_d_cache
disable_i_d_cache
stmfd sp!,{r0-r1,lr}
bl flush_i_d_cache ;将dcache上的数据flush到DDR和SRAM上
mov r1, #0x78
orr r1, r1, #0x0001
mcr p15, 0, r1, c1, c0, 0
mrc p15, 0, r0, c2, c0, 0
mov r0, r0
sub pc, pc, #4
ldmfd sp!,{r0-r1,pc}
ALIGN 4
EXPORT enable_i_d_cache
enable_i_d_cache
stmfd sp!,{r0-r1,lr}
mov r1, #0x78
;mrc p15, 0, r1, c2, c0, 0
orr r1, r1, #0x0001
orr r1, r1, #0x1000 @ Enable Icache
orr r1, r1, #0x0004 @ Enable Dcache
orr r1, r1, #0x0800 @ Enable BTB
mcr p15, 0, r1, c1, c0, 0
mrc p15, 0, r0, c2, c0, 0
mov r0, r0
sub pc, pc, #4
ldmfd sp!,{r0-r1,pc
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