Xilinx FPGA的全局时钟错误

     在ISE11.1中如果要使用某个外部信号的上升沿或下降沿来控制程序流程，因为ISE软件要求每个时钟从全局时钟端口输入，而事实上这个外部信号(如CPU的读写信号)不是全局时钟并且我们没有将它分配到全局时钟输入管脚，这时ISE软件会报告一个错误：   

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site . The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "arm_nWE" CLOCK_DEDICATED_ROUTE = FALSE; >

      怎么解决这个错误呢？

     从错误描述的最后一句话我们可以找到答案，只要在top.ucf(ISE工程顶层约束文件)的最末尾处加上一行“NET "arm_nWE" CLOCK_DEDICATED_ROUTE = FALSE;”，就能将错误变成一个警告，不影响程序的编译、布局布线等。警告内容为：
 

WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site . The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.