at91sam9260 linux 中断调用示意图（小寿原创）

 

 

 

void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)

{

       unsigned  i;
       struct at91_gpio_chip *at91_gpio, *last = NULL;

 BUG_ON(nr_banks > MAX_GPIO_BANKS);

 gpio_banks = nr_banks;

 for (i = 0; i < nr_banks; i++)
 {
        at91_gpio = &gpio_chip[i];

  at91_gpio->bank = &data[i];
  at91_gpio->chip.base = PIN_BASE + i * 32;
  at91_gpio->regbase = at91_gpio->bank->offset +
   (void __iomem *)AT91_VA_BASE_SYS;

  /* enable PIO controller's clock */
  clk_enable(at91_gpio->bank->clock);

  /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
  if (last && last->bank->id == at91_gpio->bank->id)
   last->next = at91_gpio;
  last = at91_gpio;

  gpiochip_add(&at91_gpio->chip);

}

 }

 

 

static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{

      unsigned pin;
      struct irq_desc *gpio;
      struct at91_gpio_chip *at91_gpio;
      void __iomem *pio;
      u32  isr;

 at91_gpio = get_irq_chip_data(irq);
 pio = at91_gpio->regbase;

 /* temporarily mask (level sensitive) parent IRQ */
 desc->chip->ack(irq);
 for (;;) {
  /* Reading ISR acks pending (edge triggered) GPIO interrupts.
   * When there none are pending, we're finished unless we need
   * to process multiple banks (like ID_PIOCDE on sam9263).
   */
  isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
  if (!isr)
  {
   if (!at91_gpio->next)
    break;
   at91_gpio = at91_gpio->next;
   pio = at91_gpio->regbase;
   continue;
  }

  pin = at91_gpio->chip.base;
  gpio = &irq_desc[pin];

 

  while (isr)
  {
   

if (isr & 1) 
{
    if (unlikely(gpio->depth))
    {
     /*
      * The core ARM interrupt handler lazily disables IRQs so
      * another IRQ must be generated before it actually gets
      * here to be disabled on the GPIO controller.
      */
     gpio_irq_mask(pin);
    }
    else
     generic_handle_irq(pin);
   }
   pin++;
   gpio++;
   isr >>= 1;
  }
 }
 desc->chip->unmask(irq);
 /* now it may re-trigger */

}