lpm_ram_dp (Dual-Port RAM) Megafunction

Parameterized dual-port RAM megafunction. This megafunction is provided only for backward compatibility in , , and designs; instead, Altera^® recommends using the megafunction. If you select lpm_ram_dp+ in the (Tools menu), the MegaWizard Plug-In Manager instantiates the megafunction; or the altsyncram megafunction in Stratix and Stratix GX devices. The lpm_ram_dp function uses in , , , and Mercury^™ devices, in and devices, or primitives or latch arrays in , , and devices or if the USE_EAB parameter is set to "OFF". If you need extra features, you may use the altdpram megafunction. Altera strongly recommends using synchronous rather than asynchronous RAM functions.

The Quartus® II Compiler automatically implements suitable portions of this function in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices.

Altera also recommends instantiating this function as described in .

This topic contains the following information:

• (also applies to Verilog HDL)
• (not required if the VHDL Component Declaration is used)

 

FUNCTION lpm_ram_dp (wren, data[LPM_WIDTH-1..0],
      wraddress[LPM_WIDTHAD-1..0], wrclock, wrclken, rden,
      rdaddress[LPM_WIDTHAD-1..0], rdclock, rdclken)
   WITH (LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE,
      LPM_INDATA, LPM_ADDRESS_CONTROL, LPM_RDADDRESS_CONTROL,
      LPM_OUTDATA)
   RETURNS (q[LPM_WIDTH-1..0]);

 

COMPONENT lpm_ram_dp
   GENERIC ( LPM_WIDTH: POSITIVE;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: NATURAL := 0;
      LPM_INDATA: STRING := "REGISTERED";
      LPM_OUTDATA: STRING := "REGISTERED";
      LPM_RDADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_WRADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_FILE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_RAM_DP";
      LPM_HINT: STRING := "UNUSED");
   PORT ( data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); 
      rdaddress, wraddress: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      rdclock, wrclock: IN STD_LOGIC := '0';
      rden, rdclken, wrclken: IN STD_LOGIC := '1';
      wren: IN STD_LOGIC; 
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

 

LIBRARY lpm;
USE lpm.lpm_components.all;

 

INPUT PORTS

Port Name	Required	Description	Comments
wren	Yes	Write enable input.
data[]	Yes	Data input to the memory.	Input port LPM_WIDTH wide.
wraddress[]	Yes	Write address input to the memory.	Input port LPM_WIDTHAD wide.
wrclock	No	Positive-edge-triggered clock for write operation.	If the wrclock port is used, it acts as the clock for write operation and functions as the clock signal to any registers present on the wraddress, wren, and data[] ports. For a single-clock synchronous design, you can tie rdclock and wrclock together. In ACEX 1K, APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, FLEX 10KE, and Mercury devices, the write into the internal memory array occurs during the next low period of the clock.
wrclken	No	Clock enable for wrclock.	Used by all registers clocked by wrclock. For single-clock synchronous design, you can tie rdclock and wrclock together.
rden	No	Read enable input. Disables reading when low (0). The default is 1.	In ACEX 1K, APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, FLEX 6000, FLEX 10KE, and Mercury devices, the rden port controls a latch that remembers the value last read while the rden port was high. In APEX 20K devices, the rden port becomes a power down signal. When using simulation models for other EDA simulators, the rden port always behaves as if it is targeting an ACEX 1K, APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, FLEX 6000, FLEX 10KE, or Mercury device.
rdaddress[]	Yes	Read address input to the memory.	Input port LPM_WIDTHAD wide.
rdclock	No	Positive-edge-triggered clock for read operation.	Used for registered read ports, such as q, rdaddress, and rden. If the rdclock port is used, it acts as the clock for read operation and functions as the clock signal to any registers present on the rdaddress, rden, and q[] ports.
rdclken	No	Clock enable for rdclock.	Used by all registers clocked by rdclock. For single-clock synchronous design, you can tie rdclock and wrclock together.

OUTPUT PORTS

Port Name	Required	Description	Comments
q[]	Yes	Data output from the memory.	Output port LPM_WIDTH wide.

 

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and q[] ports.
LPM_WIDTHAD	Integer	Yes	Width of the rdaddress[] and wraddress[] ports.
LPM_NUMWORDS	Integer	No	Number of words stored in memory. This value must be within the range 2 ^ WIDTHAD-1 < NUMWORDS <= 2 ^ WIDTHAD. If omitted, the default is 2 ^ WIDTHAD.
LPM_INDATA	String	No	Determines the clock used by the data port. Values are "UNREGISTERED" and "REGISTERED". The default is "REGISTERED".
LPM_OUTDATA	String	No	Determines the clock used by the q[] port. Values are "UNREGISTERED" and "REGISTERED". The default is "REGISTERED".
LPM_RDADDRESS_CONTROL	String	No	Determines the clock used by the rdaddress and rden ports. Values are "UNREGISTERED"and "REGISTERED". The default is "REGISTERED".
LPM_WRADDRESS_CONTROL	String	No	Determines the clock used by the wraddress and wren ports. Values are "UNREGISTERED" and "REGISTERED". The default is "REGISTERED".
LPM_FILE	String	No	Name of the or containing RAM initialization data (""), or . The default is "UNUSED". If omitted, contents default to all 0s. The wren port must be registered to support memory initialization.
USE_EAB	String	No	. Values are "ON", "OFF", and "UNUSED", Setting the USE_EAB parameter to OFF prevents the Quartus II software from using to implement the logic in ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can only use flipflops or latches. (The "ON" setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, and MAX 7000 devices. If you wish to use this parameter when you instantiate the function in a , you must specify it by entering the parameter name and value manually with the tab (Symbol Properties Command) or the tab (Block Properties Command). You can also use this parameter name in a or a . You must use the LPM_HINT parameter to specify the USE_EAB parameter in VHDL Design Files.

 

The lpm_ram_dp function represents asynchronous memory or memory with synchronous inputs and/or outputs.

Synchronous Write to Memory (all inputs registered)

wrclock	wrclken	wren	Function
X	L	L	No change.
not	H	H	No change.
	L	X	No change.
	H	H	The memory location pointed to by wraddress[] is loaded with data[].

For devices with ESBs or EABs, the lpm_ram_dp megafunction internally writes the data to memory while the write clock is low.

Synchronous Read from Memory

rdclock	rdclken	rden	Function
X	L	L	Device dependent.
not	H	H	No change.
	L	X	No change.
	H	H	The q[] port outputs the contents of the memory location pointed to by rdaddress[].

Totally asynchronous memory operations occur when neither rdclock nor wrclock is connected.

Asynchronous Memory Operations

wren	Function
L	No change.
H	The memory location pointed to by wraddress[] is loaded with data[] and controlled by wren. The output q[] is asynchronous and reflects the memory location pointed to by rdaddress.

 

Uses one embedded cell per data output bit for ACEX 1K, APEX 20K, APEX II, ARM-based Excalibur, FLEX 10KE, and Mercury devices; however, in FLEX 6000, MAX 3000, or MAX 7000 devices, or if the USE_EAB parameter is set to "OFF", uses one logic cell per memory bit.