关于Jtage的一些资料

1. 什么是Jtag
??JTAG(Joint Test Action Group)是一种国际标准测试协议（IEEE 1149.1兼容），主要用于芯片内部测试。现在多数的高级器件都支持JTAG协议，如DSP、FPGA器件等。标准的JTAG接口是4线：TMS、 TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。
??JTAG最初是用来对芯片进行测试的，基本原理是在器件内部定义一个TAP（Test Access Port）通过专用的JTAG测试工具对进行内部节点进行测试。JTAG测试允许多个器件通过JTAG接口串联在一起，形成一个JTAG链，能实现对各个器件分别测试。现在，JTAG接口还常用于实现ISP（In-System rogrammable），对FLASH等器件进行编程。
??JTAG编程方式是在线编程，传统生产流程中先对芯片进行预编程现再装到板上因此而改变，简化的流程为先固定器件到电路板上，再用JTAG编程，从而大大加快工程进度。JTAG接口可对PSD芯片内部的所有部件进行编程
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2. JTAG的一些说明
??通常所说的JTAG大致分两类，一类用于测试芯片的电气特性，检测芯片是否有问题；一类用于Debug；一般支持JTAG的CPU内都包含了这两个模块。
??一个含有JTAG Debug接口模块的CPU，只要时钟正常，就可以通过JTAG接口访问CPU的内部寄存器和挂在CPU总线上的设备，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）内置模块的寄存器，象UART，Timers，GPIO等等的寄存器。
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??上面说的只是JTAG接口所具备的能力，要使用这些功能，还需要软件的配合，具体实现的功能则由具体的软件决定。
??例如下载程序到RAM功能。了解SOC的都知道，要使用外接的RAM，需要参照SOC DataSheet的寄存器说明，设置RAM的基地址，总线宽度，访问速度等等。有的SOC则还需要Remap，才能正常工作。运行Firmware时，这些设置由Firmware的初始化程序完成。但如果使用JTAG接口，相关的寄存器可能还处在上电值，甚至时错误值，RAM不能正常工作，所以下载必然要失败。要正常使用，先要想办法设置RAM。在ADW中，可以在Console窗口通过Let 命令设置，在AXD中可以在Console窗口通过Set命令设置。
??下面是一个设置AT91M40800的命令序列，关闭中断，设置CS0-CS3, 并进行Remap，适用于AXD(ADS带的Debug)
??setmem 0xfffff124,0xFFFFFFFF,32 －－－关闭所有中断
??setmem 0xffe00000,0x0100253d,32 －－－设置CS0
??setmem 0xffe00004,0x02002021,32 －－－设置CS1
??setmem 0xffe00008,0x0300253d,32 －－－设置CS2
??setmem 0xffe0000C,0x0400253d,32 －－－设置CS3
??setmem 0xffe00020,1,32 －－－Remap
??如果要在ADW（SDT带的DEBUG）中使用，则要改为：
??let 0xfffff124=0xFFFFFFFF －－－关闭所有中断
??let 0xffe00000=0x0100253d －－－设置CS0
??let 0xffe00004=0x02002021 －－－设置CS1
??let 0xffe00008=0x0300253d －－－设置CS2
??let 0xffe0000C=0x0400253d －－－设置CS3
??let 0xffe00020=1 －－－Remap
??为了方便使用，可以将上述命令保存为一个文件config.ini, 在Console窗口输入 ob config.ini 即可执行。
??使用其他debug，大体类似，只是命令和命令的格式不同。
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??设置RAM时，设置的寄存器以及寄存器的值必须和要运行程序的设置一致。一般编译生成的目标文件是ELF格式，或类似的格式，包含有目标码运行地址，运行地址在Link时候确定。Debug下载程序时根据ELF文件中的地址信息下载程序到指定的地址。如果在把RAM的基地址设置为0x10000000, 而在编译的时候指定Firmware的开始地址在0x02000000, 下载的时候，目标码将被下载到0x02000000，显然下载会失败。
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??通过JTAG下载程序前应关闭所有中断，这一点和Firmware初始化时关闭中断的原因相同。在使用JTAG接口的时候，各中断的使能未知，尤其是 FLASH里有可执行码的情况，可能会有一些中断被使能。使用JTAG下载完代码，要执行时，有可能因为未完成初始化就产生了中断，导致程序异常。所以，需要先关闭中断，一般通过设置SOC的中断控制寄存器完成。
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??使用JTAG写Flash。在理论上，通过JTAG可以访问CPU总线上的所有设备，所以应该可以写FLASH，但是FLASH写入方式和RAM大不相同，需要特殊的命令，而且不同的FLASH擦除，编程命令不同，而且块的大小，数量也不同，很难提供这一项功能。所以一般Debug不提供写Flash功能，或者仅支持少量几种Flash。
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??目前就我知道的，针对 ARM，只有FlashPGM这个软件提供写FLASH功能，但使用也非常麻烦。AXD，ADW都不提供写FLASH功能。我写Flash的方法时是，自己写一个简单的程序，专门用于写目标板的FLASH，利用JTAG接口，下载到目标板，再把要烧写的目标码装成BIN格式，也下到目标板（地址和烧 FLASH的程序的地址不同），然后运行已经下载的烧FLASH的程序。使用这种方式，比起FlashPGM的写Flash，速度似乎要快一些。
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??关于简单JTAG电缆。
??目前有各种各样简单JTAG电缆，其实只是一个电平转换电路，同时还起到保护作用。JTAG的逻辑则由运行在PC上的软件实现，所以在理论上，任何一个简单 JTAG电缆，都可以支持各种应用软件，如Debug等。我就曾使用同一个JTAG电缆写Xilinx CPLD，AXD/ADW调试程序。关键再于软件的支持，大多数软件都不提供设定功能，因而只能支持某种JTAG电缆。
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??关于简单JTAG电缆的速度。
??JTAG 是串行接口，使用打印口的简单JTAG电缆，利用的是打印口的输出带锁存的特点，使用软件通过I/O产生JTAG时序。由JTAG标准决定，通过JTAG 写/读一个字节要一系列的操作，根据我的分析，使用简单JTAG电缆，利用打印口，通过JTAG输出一个字节到目标板，平均需要43个打印口I/O, 在我机器上（P4 1.7G)，每秒大约可进行660K次 I/O 操作，所以下载速度大约在660K/43, 约等于15K Byte/S. 对于其他机器，I/O速度大致相同，一般在600K ~ 800K.
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??关于如何提高JTAG下载速度。
??很明显，使用简单JTAG电缆无法提高速度。要提高速度，大致有两种办法，
??1。使用嵌入式系统提供JTAG接口，嵌入式系统和微机之间通过USB/Ethernet相连，这要求使用MCU。
??2。使用CPLD/FPGA提供JTAG接口，CPLD/FPGA和微机之间使用EPP接口（一般微机打印口都支持EPP模式），EPP接口完成微机和CPLD/FPGA之间的数据传输，CPLD/FPGA完成JTAG时序。

 

 

3. IEEE JTAG Bus Description

IEEE Std 1149.1-1990 JTAG (Joint Test Action Group); Test Access Port and Boundary-Scan Architecture. This is a serial bus with four signals: Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO). The bus is used as a test bus for the 'Boundary-Scan' of ICs, as in Design-For-Testability (DFT). To use JTAG, during the design, you most select JTAG compatible devices. ICs supporting JTAG will have the four additional pins listed above. Devices reside on the bus in a daisy chain, with TDO of one device feeding TDI of the next device. In addition to having the pins listed above each device most have a Boundary-Scan Register. The Boundary-Scan Register may be used to test the interconnection between ICs [Chip-to-Chip] or test with in the IC. Boundary-scan tests can be used to check continuity between devices. Continuity checks on PWB nets may be performed by sending out a know pattern and receiving that same pattern at the input to another IC(s). Not receiving the test signal or pattern would indicate a broken PWB trace, a failed IC, or cold solder joint.

TCK: [Test Clock] has noting to do with the board or system clock. The Test Clock is used to load the test mode data from the TMS pin, and the test data on the TDI pin [on the rising edge]. On the falling edge test clock outputs the test data on the TDO pin.

TMS: [Test Mode Select Input] controls the operation of the test logic, by receiving the incoming data]. The value at the input on the rising edge of the clock controls the movement through the states of the TAP controller. The TMS line has an internal pull-up, so the input is high with no input.

TDI: [Test Data Input] receives serial input data which is either feed to the test data registers or instruction register, but depends on the state of the TAP controller. The TDI line has an internal pull-up, so the input is high with no input.

TDO: [Test Data Output] outputs serial data which comes from either the test data registers or instruction register, but depends on the state of the TAP controller. Data applies to the TDI pin will appear at the TDO pin but may be shifted of a number of clock cycles, depending on the length of the internal register. The TDO pin is high-Impedance.

TRST: [Test Rest] will asynchronously reset the JTAG test logic. The logic is reset {with TRST) regardless of the state of TMS or TCLK.

Note. BSDL [Boundary Scan Description Language] is a subset of the VHDL standard.
Any manufacturer of a JTAG compliant device must provide a BSDL file for that device. The BSDL file contains information on the function of each of the pins on the device - which are used as I/Os, power or ground. BSDL files describe the Boundary Scan architecture of a JTAG-compliant device, and are written in VHDL. The BSDL file includes:
... 1. Entity Declaration: The entity declaration is a VHDL construct that is used to identify the name of the device that is described by the BSDL file.
... 2. Generic Parameter: The Generic parameter specifies which package is described by the BSDL file.
... 3. Logical Port Description: lists all of the pads on a device, and states whether that pin is an input(in bit;), output(out bit;), bidirectional (inout bit;) or unavailable for boundary scan (linkage bit;).
... 4. Package Pin Mapping: The Package Pin Mapping shows how the pads on the device die are wired to the pins on the device package.
... 5. Use statements: The use statement calls VHDL packages that contain attributes, types, constants, etc. that are referenced in the BSDL File.
... 6. Scan Port Identification: The Scan Port Identification identifies the JTAG pins: TDI, TDO, TMS, TCK and TRST (if used).
... 7. TAP description: provides additional information on the device's JTAG logic; the Instruction Register length, Instruction Opcodes, device IDCODE, etc. These characteristics are device specific.
... 8. Boundary Register description: provides the structure of the Boundary Scan cells on the device. Each pin on a device may have up to three Boundary Scan cells, each cell consisting of a register and a latch.

IEEE Std 1149.5-1995 IEEE Standard for Module Test and Maintenance Bus (MTM-Bus) Protocol
Specifies a serial, backplane, test and maintenance bus (MTM-Bus)..... between a Test Control Master and up to 250 Slave modules.
The interface has 5 signals:
... MTM Clock (MCLK)
... MTM Control (MCTL)
... MTM Master Data (MMD)
... MTM Slave Data (MSD)
... MTM Pause Request (MPR).
This specification is used at the Board level while 1149.1 is used at the chip level.

IEEE Std 1532 Boundary-Scan-based In System Configuration of Programmable Devices; is a follow on or extension to JTAG. IEEE 1532 is a superset of the IEEE 1149.1 JTAG standard. IEEE 1532 also provides additional flexibility for configuring Programmable Logic Devices [FPGA, PLDs].

Standards:
IEEE 1149.1 deals with test for digital assemblies
IEEE 1149.4 deals with test for mixed signal and analog assemblies
IEEE 1149.5 deals with test at system level
IEEE 1532 is a derivative standard for in-system programming of digital devices

Definitions:
ATE: Automatic Test Equipment
BIT: Built-In-Test
BSDL: Boundary Scan Description Language
BSR: Boundary Scan Register
DFT: Design-For-Test
JTAG: Joint Test Action Group
IC: Integrated Circuit

Engineering Design Key words for this page: JTAG Bus, IEEE-std-1149.1, Boundary Scan, JTAG, Scan, Bscan, Boundary Scan, BST, Board-Under-Test, Testability, Joint Test Action Group, Integrated Circuit, IC Bus, Chip-to-Chip, Electrical layer, Multi-Drop, Standard, Serial Communications interface, Interface Standard Data Bus, Standard, Specification, Spec, Validate, IC, Physical Interface, Description, Fault isolation.