怎么介绍?
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2010-06-19 03:42:17
In earlier examples we either explicitly spelled out how each target is ``made'' from the prerequisites or relied on make magic to do the right thing.
This section looks into how to write and provide suffix rules, which are also called ``implicit rules''.
Writing your own rules frees the Makefile from being intimately dependent on any particular make or platform and can shorten Makefiles for large projects.
Suffix rules are, in a sense, generic rules for converting, say .c files to .o files.
Suffix rules are of the form:
Suffixes can be any string of characters, and by convention usually include a ``dot'' (.), but does not require it. The allowed suffixes are given by the .SUFFIXES fake target.s1s2 :
commands to get s2 from s1
The following is a reworking of an earlier example with helpful comments:
CC = gcc
CFLAGS = -g
LD = $(CC)
LDFLAGS =
RM = rm
EXE = mainx
SRCS = main.c sub1.c sub2.c sub3.c
OBJS = ${SRCS:.c=.o}
# clear out all suffixes
.SUFFIXES:
# list only those we use
.SUFFIXES: .o .c
# define a suffix rule for .c -> .o
.c.o :
$(CC) $(CFLAGS) -c $<
# default target by convention is ``all''
all : $(EXE)
$(EXE) : $(OBJS)
$(LD) -o $@ $(OBJS)
$(OBJS) : proj.h
clean :
-$(RM) -f $(EXE) $(OBJS)
Strongly recommend that you write your own suffix rules for all those used within the software project. The need for this is demonstrated by the lack of consistency in macro names for the Fortran compiler shown in the last section.
However, if you are only using C and the associated tools (lex, yacc, ar, and ld) then the default macros and suffix rules are probably sufficient since they are fairly standard.
Looking at the predefined suffix rules are useful for composing your own and to observe which macros are used for each compiling tool.% make -p -f /dev/null