前言
之前没有写过博客,这是第一次写,希望能记录下自己的开发流程,如果能给一些人一些参考,那是荣幸之至,如果有疏漏错误之处,大家可以互相讨论。
Zynq是一款比较强大的SOC,内部包含FPGA和Cortex-A9双核的ARM,我的这个设计就是用Zedboard开发板,搭配一个OV7725的cmos图像传感器,实现图像的采集和简单的传输,具体功能包括:图像采集,Bayer图像转RGB888图像,自制VDMA模块,VGA controller,Linux系统视频发送,Linux虚拟机QT客户端视频显示,后续可能还会再添加一些功能模块。其中OV7725寄存器初始化,Bayer图像转RGB888图像,VGA controller参考了crazybingo的设计。
这里不再赘述Zynq内部结构等,而是直接针对具体应用,如果有不明白的可以看官方手册或者给我留言。
硬件设计
先上一张图片
使用了Zedboard的pmod接口,做了适当的修改,也可以使用杜邦线连接,管脚约束如下:
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set_property PACKAGE_PIN Y9 [get_ports ext_clk]
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set_property IOSTANDARD LVCMOS25 [get_ports ext_clk]
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#
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#VGA
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#
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set_property PACKAGE_PIN V20 [get_ports {vga_r[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_r[0]}]
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set_property PACKAGE_PIN U20 [get_ports {vga_r[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_r[1]}]
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set_property PACKAGE_PIN V19 [get_ports {vga_r[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_r[2]}]
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set_property PACKAGE_PIN V18 [get_ports {vga_r[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_r[3]}]
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set_property PACKAGE_PIN AB22 [get_ports {vga_g[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_g[0]}]
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set_property PACKAGE_PIN AA22 [get_ports {vga_g[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_g[1]}]
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set_property PACKAGE_PIN AB21 [get_ports {vga_g[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_g[2]}]
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set_property PACKAGE_PIN AA21 [get_ports {vga_g[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_g[3]}]
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set_property PACKAGE_PIN Y21 [get_ports {vga_b[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_b[0]}]
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set_property PACKAGE_PIN Y20 [get_ports {vga_b[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_b[1]}]
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set_property PACKAGE_PIN AB20 [get_ports {vga_b[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_b[2]}]
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set_property PACKAGE_PIN AB19 [get_ports {vga_b[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vga_b[3]}]
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set_property PACKAGE_PIN AA19 [get_ports vga_hs]
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set_property IOSTANDARD LVCMOS25 [get_ports vga_hs]
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set_property PACKAGE_PIN Y19 [get_ports vga_vs]
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set_property IOSTANDARD LVCMOS25 [get_ports vga_vs]
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set_property PACKAGE_PIN Y10 [get_ports {cmos_data[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[0]}]
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set_property PACKAGE_PIN AB9 [get_ports {cmos_data[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[1]}]
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set_property PACKAGE_PIN AA9 [get_ports {cmos_data[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[2]}]
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set_property PACKAGE_PIN AA8 [get_ports {cmos_data[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[3]}]
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set_property PACKAGE_PIN W12 [get_ports {cmos_data[4]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[4]}]
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set_property PACKAGE_PIN V12 [get_ports {cmos_data[5]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[5]}]
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set_property PACKAGE_PIN W11 [get_ports {cmos_data[6]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[6]}]
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set_property PACKAGE_PIN W10 [get_ports {cmos_data[7]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {cmos_data[7]}]
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set_property PACKAGE_PIN AB10 [get_ports cmos_sclk]
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set_property IOSTANDARD LVCMOS25 [get_ports cmos_sclk]
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set_property PACKAGE_PIN AA11 [get_ports cmos_sdat]
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set_property IOSTANDARD LVCMOS25 [get_ports cmos_sdat]
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set_property PACKAGE_PIN V9 [get_ports cmos_pclk]
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set_property IOSTANDARD LVCMOS25 [get_ports cmos_pclk]
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set_property PACKAGE_PIN V10 [get_ports cmos_xclk]
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set_property IOSTANDARD LVCMOS25 [get_ports cmos_xclk]
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set_property PACKAGE_PIN V8 [get_ports cmos_vsync]
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set_property IOSTANDARD LVCMOS25 [get_ports cmos_vsync]
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set_property PACKAGE_PIN W8 [get_ports cmos_href]
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set_property IOSTANDARD LVCMOS25 [get_ports cmos_href]
附上一张成像效果图
接下来的文章中就开始整个系统设计
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