switch_mm

static inline void
switch_mm(struct mm_struct *prev, struct mm_struct *next,
      struct task_struct *tsk)
{
#ifdef CONFIG_MMU
    unsigned int cpu = smp_processor_id();

#ifdef CONFIG_SMP
    /* check for possible thread migration */
    if (!cpumask_empty(mm_cpumask(next)) &&
        !cpumask_test_cpu(cpu, mm_cpumask(next)))
        __flush_icache_all();
#endif
    if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
#ifdef CONFIG_SMP
        struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
        *crt_mm = next;
#endif
        check_context(next);
        cpu_switch_mm(next->pgd, next);
        if (cache_is_vivt())
            cpumask_clear_cpu(cpu, mm_cpumask(prev));
    }
#endif
}


#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)

#define cpu_do_switch_mm        processor.switch_mm

arch/arm/mm/proc-arm926.s:

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
    .align    5
ENTRY(cpu_arm926_switch_mm)
#ifdef CONFIG_MMU
    mov    ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
    mcr    p15, 0, ip, c7, c6, 0        @ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:    mrc    p15, 0, r15, c7, c14, 3     @ test,clean,invalidate
    bne    1b
#endif
    mcr    p15, 0, ip, c7, c5, 0        @ invalidate I cache
    mcr    p15, 0, ip, c7, c10, 4        @ drain WB
    mcr    p15, 0, r0, c2, c0, 0        @ load page table pointer
    mcr    p15, 0, ip, c8, c7, 0        @ invalidate I & D TLBs
#endif
    mov    pc, lr