KL系列 LPTMR定时器应用笔记

项目上用了KL芯片，其中需要一个1ms的周期中断，采用了LPTMR定时器来完成驱动，配置如下：

WORD32 Timer_Init(WORD16 wTime)
{
    WORD32 dwData = 0;                       // For temp value of register

    if (MAX_TIME_PERIOD_MS < wTime)          // If the period time is bigger than 65(65535)
    {
        return SW_ERR;                       // Then return with error flag;
    }
    if (0 == wTime)                          // If the period time is 0, than turn off LPTMR
    {
        LPTMR0_CSR |= LPTMR_CSR_TEN_MASK;    // It is the way to turn OFF LPTMR
        return SW_OK;
    }

    MCG_SC &= (~MCG_SC_FCRDIV_MASK);         // Do this before set value of FCRDIV to evoid wrong masking
    MCG_SC |= MCG_SC_FCRDIV(2);              // We choose to divided clock by 4
    MCG_C2 |= MCG_C2_IRCS_MASK;              // And we choose the fast internal refenced clock(4MHz),
                                             // So final clock is 1Mhz.
    MCG_C1    |= MCG_C1_IRCLKEN_MASK;        // Then turn on MCGIRCLK and it works even in stop mode
    SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;       // Enable LPTMR software accessing

    LPTMR0_CSR &= ~LPTMR_CSR_TEN_MASK;       // Turn off LPTMR before LPTMR register configration
    dwData     |= (LPTMR_CSR_TIE_MASK\
                  |LPTMR_CSR_TCF_MASK);      // We do this to reduce operations of register to save time
    LPTMR0_CSR  = dwData;                    // In this case, we just operate register for once.
    LPTMR0_PSR |= LPTMR_PSR_PBYP_MASK;       // We do not need to divided the clock any more here
    LPTMR0_PSR &= (~LPTMR_PSR_PCS_MASK);     // Choose MCGIRCLK as the clock source (1MHz)
    LPTMR0_CMR  = (wTime*1000);              // Then turn it as a period in 1ms

    LPTMR0_CSR |= LPTMR_CSR_TEN_MASK;        // After all, we turn on LPTMR and start counting
    return SW_OK;                            // That is all
}

I write the comments with English, please forgive me for my zhuangbility. Everybody have fun^-^

Summry: The MCGIRCLK is an internal clock with two clock sources : 32KHz and 4MHz, there seem to be fixed, so you can use them without any care of you crystal clock. In this case, it is a good way for you to realise a driver because it is fixed. May we still need to modify something for other situations, but it works for my application. By the way, 32KHz and 4MHz can be chose by the field IRCS of the register MCG_C2, clear this field will choose the slow clock source 32KHz ,or you can get a 4MHz as mentioned fast clock source by setting this field. Do I need to explain what is "clear" and "set"? I will never tell you that "clear" is writing "0" to a field and "set" is writing "1" to this field.