uPP通信（2）---FPGA篇

 

系统架构

 

本系统组成如下图，FPGA挨个读取24个AD通道中的数据，然后通过UPP方式传送给OMAPL138中的DSP核，经过一系列运算，DSP核通过DSPLINK方式将数据送到ARM核。

 

 

FPGA数据读取、存储、传送、数据识别问题

 

因为OMAPL138需要识别传送上来的数据是对应哪个通道的。所以FPGA对数据必须做一些处理以便于OMAPL138对数据分门别类。

方法一：

在FPGA中生成一个FIFO，挨个读取24个AD通道中的数据按次序存放到FIFO中，FIFO中存放满预定大小的数据量时再上传给OMAPL138，这样OMAPL138就知道第一个数据是对应通道1的，第二个数据是对应通道2的。

优点：简单，容易实现

缺点：如果其中一个数据出错或者漏传，那后面的一大堆数据都会被错误归类。

方法二：

AD通道输出数据是16位，将其扩展为32位，高16位作为标志位。例如，如果第一个AD通道读出来的0xDE33,那扩展为32位时其数据为0x0001DE33。OMAPL138通过其高16位辨别这个数据是哪个通道的。

优点：不再像方法一担心数据传错了，传错也不会危害到整体。

缺点：OMAPL138的UPP通信时16位的数据线，原来是需要传送数据，现在还要传送标志数据，这样直接导致传输效率打5折。但是对于能够到达150MB/s吞吐量的UPP来说，就算传输只能达到50%，也是能满足我目前这个系统的。

 

 

读取AD：

以下是读取ad的代码，状态机的状态比较多，比较麻烦。

module ads_ddio (
                        clk,
                        rst,
                        eoc,
                        datain,
                        dataout,
                        f_ncs,
                        f_nrd,
                        fifo_wr,
                        f_c1,
                        f_c2,
                        f_c3,
                        f_c4,
                        f_c5,
                        f_c6
                    );


input             clk,rst;
input[1:0]        eoc;
input[15:0]     datain;
output             f_c1, f_c2, f_c3, f_c4, f_c5, f_c6;
output[1:0]           f_ncs;
output[1:0]             f_nrd;
output         fifo_wr;
output[31:0]     dataout;


reg[7:0] counter;
reg[31:0] data_reg;
reg state;
reg[1:0]  eoc1;
reg[5:0] cstate,nstate;
reg[1:0] f_nrd_reg,f_ncs_reg;
reg fifo_wr_reg;

parameter     SET_COUNT           = 8'hff,

                SET_CSRD_C1UA   = 8'd23,
                SET_DATA_C1UA   = 8'd24,
                SET_CSRD_C1UB   = 8'd26,
                SET_DATA_C1UB   = 8'd27,
                SET_CSRD_C1UC   = 8'd29,
                SET_DATA_C1UC   = 8'd30,
                SET_CSRD_C1IA   = 8'd32,
                SET_DATA_C1IA   = 8'd33,
                SET_CSRD_C1IB   = 8'd35,
                SET_DATA_C1IB   = 8'd36,
                SET_CSRD_C1IC   = 8'd38,
                SET_DATA_C1IC   = 8'd39,

                SET_CSRD_C2UA   = 8'd41,
                SET_DATA_C2UA   = 8'd42,
                SET_CSRD_C2UB   = 8'd44,
                SET_DATA_C2UB   = 8'd45,
                SET_CSRD_C2UC   = 8'd47,
                SET_DATA_C2UC   = 8'd48,
                SET_CSRD_C2IA   = 8'd50,
                SET_DATA_C2IA   = 8'd51,
                SET_CSRD_C2IB   = 8'd53,
                SET_DATA_C2IB   = 8'd54,
                SET_CSRD_C2IC   = 8'd56,
                SET_DATA_C2IC   = 8'd57,

                SET_FIFO_DATA   = 8'd60,  //上个状态+3

                SET_IDLE            = 8'd62;


parameter      IDLE                  = 6'd0,
                CSRDN_C1UA        = 6'd1,
                DATA_C1UA         = 6'd2,
                DATA1_C1UA     = 6'd3,
                CSRDN_C1UB        = 6'd4,
                DATA_C1UB         = 6'd5,
                DATA1_C1UB     = 6'd6,
                CSRDN_C1UC        = 6'd7,
                DATA_C1UC         = 6'd8,
                DATA1_C1UC     = 6'd9,
                CSRDN_C1IA        = 6'd10,
                DATA_C1IA         = 6'd11,
                DATA1_C1IA     = 6'd12,
                CSRDN_C1IB        = 6'd13,
                DATA_C1IB         = 6'd14,
                DATA1_C1IB     = 6'd15,
                CSRDN_C1IC        = 6'd16,
                DATA_C1IC         = 6'd17,
                DATA1_C1IC     = 6'd18,

                CSRDN_C2UA        = 6'd19,
                DATA_C2UA         = 6'd20,
                DATA1_C2UA     = 6'd21,
                CSRDN_C2UB        = 6'd22,
                DATA_C2UB         = 6'd23,
                DATA1_C2UB     = 5'd24,
                CSRDN_C2UC        = 6'd25,
                DATA_C2UC         = 6'd26,
                DATA1_C2UC     = 6'd27,
                CSRDN_C2IA        = 6'd28,
                DATA_C2IA         = 6'd29,
                DATA1_C2IA     = 6'd30,
                CSRDN_C2IB        = 6'd31,
                DATA_C2IB         = 6'd32,
                DATA1_C2IB     = 6'd33,
                CSRDN_C2IC        = 6'd34,
                DATA_C2IC         = 6'd35,
                DATA1_C2IC     = 6'd36,
                FIFO_DATA      = 6'd37;


wire csrd_n_c1ua_req;
wire csrd_n_c1ub_req;
wire csrd_n_c1uc_req;
wire csrd_n_c1ia_req;
wire csrd_n_c1ib_req;
wire csrd_n_c1ic_req;

wire csrd_n_c2ua_req;
wire csrd_n_c2ub_req;
wire csrd_n_c2uc_req;
wire csrd_n_c2ia_req;
wire csrd_n_c2ib_req;
wire csrd_n_c2ic_req;


wire data_c1ua_req;
wire data_c1ub_req;
wire data_c1uc_req;
wire data_c1ia_req;
wire data_c1ib_req;
wire data_c1ic_req;

wire data_c2ua_req;
wire data_c2ub_req;
wire data_c2uc_req;
wire data_c2ia_req;
wire data_c2ib_req;
wire data_c2ic_req;

wire fifo_data_req;

wire idle_req;

assign f_c1  = 1'b1;
assign f_c2  = 1'b0;
assign f_c3  = 1'b1;
assign f_c4  = 1'b0;
assign f_c5  = 1'b0;
assign f_c6  = 1'b0;

assign dataout = data_reg;

assign csrd_n_c1ua_req = (counter == SET_CSRD_C1UA);
assign csrd_n_c1ub_req = (counter == SET_CSRD_C1UB);
assign csrd_n_c1uc_req = (counter == SET_CSRD_C1UC);
assign csrd_n_c1ia_req = (counter == SET_CSRD_C1IA);
assign csrd_n_c1ib_req = (counter == SET_CSRD_C1IB);
assign csrd_n_c1ic_req = (counter == SET_CSRD_C1IC);

assign csrd_n_c2ua_req = (counter == SET_CSRD_C2UA);
assign csrd_n_c2ub_req = (counter == SET_CSRD_C2UB);
assign csrd_n_c2uc_req = (counter == SET_CSRD_C2UC);
assign csrd_n_c2ia_req = (counter == SET_CSRD_C2IA);
assign csrd_n_c2ib_req = (counter == SET_CSRD_C2IB);
assign csrd_n_c2ic_req = (counter == SET_CSRD_C2IC);


assign data_c1ua_req = (counter == SET_DATA_C1UA);
assign data_c1ub_req = (counter == SET_DATA_C1UB);
assign data_c1uc_req = (counter == SET_DATA_C1UC);
assign data_c1ia_req = (counter == SET_DATA_C1IA);
assign data_c1ib_req = (counter == SET_DATA_C1IB);
assign data_c1ic_req = (counter == SET_DATA_C1IC);

assign data_c2ua_req = (counter == SET_DATA_C2UA);
assign data_c2ub_req = (counter == SET_DATA_C2UB);
assign data_c2uc_req = (counter == SET_DATA_C2UC);
assign data_c2ia_req = (counter == SET_DATA_C2IA);
assign data_c2ib_req = (counter == SET_DATA_C2IB);
assign data_c2ic_req = (counter == SET_DATA_C2IC);


assign fifo_data_req = (counter == SET_FIFO_DATA);
assign idle_req = (counter == SET_IDLE);
assign f_nrd[0] = (cstate == DATA_C1UA || cstate == CSRDN_C1UA ||  cstate == DATA_C1UB || cstate == CSRDN_C1UB ||  cstate == DATA_C1UC || cstate == CSRDN_C1UC ||  cstate == DATA_C1IA || cstate == CSRDN_C1IA ||  cstate == DATA_C1IB || cstate == CSRDN_C1IB ||  cstate == DATA_C1IC || cstate == CSRDN_C1IC ) ?  f_nrd_reg[0] : 1'b1;
assign f_ncs[0] = (cstate == DATA_C1UA || cstate == CSRDN_C1UA ||  cstate == DATA_C1UB || cstate == CSRDN_C1UB ||  cstate == DATA_C1UC || cstate == CSRDN_C1UC ||  cstate == DATA_C1IA || cstate == CSRDN_C1IA ||  cstate == DATA_C1IB || cstate == CSRDN_C1IB ||  cstate == DATA_C1IC || cstate == CSRDN_C1IC ) ?  f_ncs_reg[0] : 1'b1;
assign f_nrd[1] = (cstate == DATA_C2UA || cstate == CSRDN_C2UA ||  cstate == DATA_C2UB || cstate == CSRDN_C2UB ||  cstate == DATA_C2UC || cstate == CSRDN_C2UC ||  cstate == DATA_C2IA || cstate == CSRDN_C2IA ||  cstate == DATA_C2IB || cstate == CSRDN_C2IB ||  cstate == DATA_C2IC || cstate == CSRDN_C2IC ) ?  f_nrd_reg[1] : 1'b1;
assign f_ncs[1] = (cstate == DATA_C2UA || cstate == CSRDN_C2UA ||  cstate == DATA_C2UB || cstate == CSRDN_C2UB ||  cstate == DATA_C2UC || cstate == CSRDN_C2UC ||  cstate == DATA_C2IA || cstate == CSRDN_C2IA ||  cstate == DATA_C2IB || cstate == CSRDN_C2IB ||  cstate == DATA_C2IC || cstate == CSRDN_C2IC ) ?  f_ncs_reg[1] : 1'b1;
assign fifo_wr = ( /* cstate ==DATA_C1UA ||*/ cstate == DATA_C1UB || cstate == DATA_C1UC || cstate == DATA_C1IA || cstate == DATA_C1IB || cstate == DATA_C1IC || cstate == DATA_C2UA || cstate == DATA_C2UB || cstate == DATA_C2UC || cstate == DATA_C2IA || cstate == DATA_C2IB || cstate == DATA_C2IC ||cstate == FIFO_DATA ) ? fifo_wr_reg : 1'b0;



always @ (posedge clk or negedge rst)
    if(!rst)
        cstate <= IDLE;
    else
        cstate <= nstate;

always @ (cstate or fifo_data_req or csrd_n_c1ua_req or data_c1ub_req or csrd_n_c1uc_req or data_c1ia_req or data_c1ib_req or data_c1ic_req  or csrd_n_c2ua_req or data_c2ub_req or csrd_n_c2uc_req or data_c2ia_req or data_c2ib_req or data_c2ic_req)
    case (cstate)
        IDLE:
            if(csrd_n_c1ua_req)
                nstate <= CSRDN_C1UA;
            else
                nstate <= IDLE;
         CSRDN_C1UA:
            if(data_c1ua_req)
                nstate <= DATA_C1UA;
            else
                nstate <= CSRDN_C1UA;
         DATA_C1UA:
            nstate <= DATA1_C1UA;
         DATA1_C1UA:
            if(csrd_n_c1ub_req)
                nstate <= CSRDN_C1UB;
            else
                nstate <= DATA1_C1UA;
         CSRDN_C1UB:
            if(data_c1ub_req)
                nstate <= DATA_C1UB;
            else
                nstate <= CSRDN_C1UB;
         DATA_C1UB:
            nstate <= DATA1_C1UB;
         DATA1_C1UB:
            if(csrd_n_c1uc_req)
                nstate <= CSRDN_C1UC;
            else
                nstate <= DATA1_C1UB;
         CSRDN_C1UC:
            if(data_c1uc_req)
                nstate <= DATA_C1UC;
            else
                nstate <= CSRDN_C1UC;
         DATA_C1UC:
            nstate <= DATA1_C1UC;
         DATA1_C1UC:
            if(csrd_n_c1ia_req)
                nstate <= CSRDN_C1IA;
            else
                nstate <= DATA1_C1UC;
         CSRDN_C1IA:
            if(data_c1ia_req)
                nstate <= DATA_C1IA;
            else
                nstate <= CSRDN_C1IA;
         DATA_C1IA:
            nstate <= DATA1_C1IA;
         DATA1_C1IA:
            if(csrd_n_c1ib_req)
                nstate <= CSRDN_C1IB;
            else
                nstate <= DATA1_C1IA;
         CSRDN_C1IB:
            if(data_c1ib_req)
                nstate <= DATA_C1IB;
            else
                nstate <= CSRDN_C1IB;
         DATA_C1IB:
            nstate <= DATA1_C1IB;
         DATA1_C1IB:
            if(csrd_n_c1ic_req)
                nstate <= CSRDN_C1IC;
            else
                nstate <= DATA1_C1IB;
         CSRDN_C1IC:
            if(data_c1ic_req)
                nstate <= DATA_C1IC;
            else
                nstate <= CSRDN_C1IC;
         DATA_C1IC:
            nstate <= DATA1_C1IC;
         DATA1_C1IC:
            if(csrd_n_c2ua_req)
                nstate <= CSRDN_C2UA;
            else
                nstate <= DATA1_C1IC;
/////////////////////////////////////////////////////////////////
         CSRDN_C2UA:
            if(data_c2ua_req)
                nstate <= DATA_C2UA;
            else
                nstate <= CSRDN_C2UA;
         DATA_C2UA:
            nstate <= DATA1_C2UA;
         DATA1_C2UA:
            if(csrd_n_c2ub_req)
                nstate <= CSRDN_C2UB;
            else
                nstate <= DATA1_C2UA;
         CSRDN_C2UB:
            if(data_c2ub_req)
                nstate <= DATA_C2UB;
            else
                nstate <= CSRDN_C2UB;
         DATA_C2UB:
            nstate <= DATA1_C2UB;
         DATA1_C2UB:
            if(csrd_n_c2uc_req)
                nstate <= CSRDN_C2UC;
            else
                nstate <= DATA1_C2UB;
         CSRDN_C2UC:
            if(data_c2uc_req)
                nstate <= DATA_C2UC;
            else
                nstate <= CSRDN_C2UC;
         DATA_C2UC:
            nstate <= DATA1_C2UC;
         DATA1_C2UC:
            if(csrd_n_c2ia_req)
                nstate <= CSRDN_C2IA;
            else
                nstate <= DATA1_C2UC;
         CSRDN_C2IA:
            if(data_c2ia_req)
                nstate <= DATA_C2IA;
            else
                nstate <= CSRDN_C2IA;
         DATA_C2IA:
            nstate <= DATA1_C2IA;
         DATA1_C2IA:
            if(csrd_n_c2ib_req)
                nstate <= CSRDN_C2IB;
            else
                nstate <= DATA1_C2IA;
         CSRDN_C2IB:
            if(data_c2ib_req)
                nstate <= DATA_C2IB;
            else
                nstate <= CSRDN_C2IB;
         DATA_C2IB:
            nstate <= DATA1_C2IB;
         DATA1_C2IB:
            if(csrd_n_c2ic_req)
                nstate <= CSRDN_C2IC;
            else
                nstate <= DATA1_C2IB;
         CSRDN_C2IC:
            if(data_c2ic_req)
                nstate <= DATA_C2IC;
            else
                nstate <= CSRDN_C2IC;
         DATA_C2IC:
            nstate <= DATA1_C2IC;
         DATA1_C2IC:
            if(fifo_data_req)
                nstate <= FIFO_DATA;
            else
                nstate <= DATA1_C2IC;
         FIFO_DATA:
            if(idle_req)
                nstate <= IDLE;
            else
                nstate <= IDLE;
/*
         DATA1_C1UB:
            if(idle_req)
                nstate <= IDLE;
            else
                nstate <= DATA1_C1UB;
*/
         default:
            nstate <= IDLE;
    endcase

always @ (posedge clk)
    begin
        case (cstate)
            FIFO_DATA:
                    fifo_wr_reg <= 1'b1;   //把最后一个数据输出到fifo中详细请看signaltap2
            DATA_C1UA:
                begin
                    data_reg <= {16'h11,datain};
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
    //                fifo_wr_reg <= 1'b1;     //第一个数据刚好读到寄存器，还没放到fifo的总线上，所以第一个DATA状态不要拉高，详细请看signaltap2
                end
            CSRDN_C1UA:
                begin
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                end
            DATA1_C1UA:
                begin
                    f_nrd_reg[0] <= 1'b1;
                    f_ncs_reg[0] <= 1'b1;
                end
            DATA_C1UB:
                begin
                    data_reg <= {16'h12,datain};
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C1UB:
                begin
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                end
            DATA1_C1UB:
                begin
                    f_nrd_reg[0] <= 1'b1;
                    f_ncs_reg[0] <= 1'b1;
                end
            DATA_C1UC:
                begin
                    data_reg <= {16'h13,datain};
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C1UC:
                begin
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                end
            DATA1_C1UC:
                begin
                    f_nrd_reg[0] <= 1'b1;
                    f_ncs_reg[0] <= 1'b1;
                end
            DATA_C1IA:
                begin
                    data_reg <= {16'h14,datain};
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C1IA:
                begin
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                end
            DATA1_C1IA:
                begin
                    f_nrd_reg[0] <= 1'b1;
                    f_ncs_reg[0] <= 1'b1;
                end
            DATA_C1IB:
                begin
                    data_reg <= {16'h15,datain};
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C1IB:
                begin
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                end
            DATA1_C1IB:
                begin
                    f_nrd_reg[0] <= 1'b1;
                    f_ncs_reg[0] <= 1'b1;
                end
            DATA_C1IC:
                begin
                    data_reg <= {16'h16,datain};
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C1IC:
                begin
                    f_nrd_reg[0] <= 1'b0;
                    f_ncs_reg[0] <= 1'b0;
                end
            DATA1_C1IC:
                begin
                    f_nrd_reg[0] <= 1'b1;
                    f_ncs_reg[0] <= 1'b1;
                end
///////////////////////////////////////
            DATA_C2UA:
                begin
                    data_reg <= {16'h21,datain};
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C2UA:
                begin
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                end
            DATA1_C2UA:
                begin
                    f_nrd_reg[1] <= 1'b1;
                    f_ncs_reg[1] <= 1'b1;
                end
            DATA_C2UB:
                begin
                    data_reg <= {16'h22,datain};
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C2UB:
                begin
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                end
            DATA1_C2UB:
                begin
                    f_nrd_reg[1] <= 1'b1;
                    f_ncs_reg[1] <= 1'b1;
                end
            DATA_C2UC:
                begin
                    data_reg <= {16'h23,datain};
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C2UC:
                begin
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                end
            DATA1_C2UC:
                begin
                    f_nrd_reg[1] <= 1'b1;
                    f_ncs_reg[1] <= 1'b1;
                end
            DATA_C2IA:
                begin
                    data_reg <= {16'h24,datain};
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C2IA:
                begin
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                end
            DATA1_C2IA:
                begin
                    f_nrd_reg[1] <= 1'b1;
                    f_ncs_reg[1] <= 1'b1;
                end
            DATA_C2IB:
                begin
                    data_reg <= {16'h25,datain};
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C2IB:
                begin
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                end
            DATA1_C2IB:
                begin
                    f_nrd_reg[1] <= 1'b1;
                    f_ncs_reg[1] <= 1'b1;
                end
            DATA_C2IC:
                begin
                    data_reg <= {16'h26,datain};
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                    fifo_wr_reg <= 1'b1;
                end
            CSRDN_C2IC:
                begin
                    f_nrd_reg[1] <= 1'b0;
                    f_ncs_reg[1] <= 1'b0;
                end
            DATA1_C2IC:
                begin
                    f_nrd_reg[1] <= 1'b1;
                    f_ncs_reg[1] <= 1'b1;
                end
///////////////////////////////////////
            IDLE:
                begin
                    data_reg <= {16'h88,16'h00};
                //    fifo_wr_reg <= 1'b1;
                end
        default: ;
        endcase
    end



always @ (posedge clk)
    if(!rst)
        begin
            counter <=  8'd0;
            eoc1    <=  1'd0;
            state   <=  1'd0;
        end
    else
        begin
            eoc1       <=  eoc;
            case (state)
                    1'd0:
                            begin
                                    counter <= 8'd0;
                                    if(eoc & (~eoc1))
                                            begin
                                                    state     <=     1'd1;
                                                    counter    <=        counter + 8'd1;
                                            end
                            end
                    1'd1:
                            begin
                                    if(counter == SET_COUNT)
                                            begin
                                                    state     <=     1'd0;
                                                    counter     <=     8'd0;
                                            end
                                    else
                                            if(eoc & (~eoc1))
                                                    begin
                                                            counter <= 8'd0;
                                                    end
                                            else
                                                    counter <=     counter + 8'd1;
                            end
                endcase
       end
endmodule

FIFO传送判断条件

module fifo_switch(
                        clk,
                        rst,
                        almost_full,
                        empty,
                        rdreq
                   );
input clk,rst;
input almost_full,empty;
output rdreq;

reg state = 1'b0;

reg almost_full_p, empty_p;


assign rdreq = state ? 1'b1 : 1'b0;

always @ (posedge clk)
    if(!rst)
        begin
            almost_full_p <= 1'b0;
            empty_p    <= 1'b0;
        end
    else
        begin
            almost_full_p <= almost_full;
            empty_p <= empty;
        end

always @ (posedge clk)
    case (state)
        1'b0:
            if(almost_full & ~almost_full_p)
                state <= 1'b1;
        1'b1:
            if(empty & ~empty_p)
                state <= 1'b0;
    endcase


endmodule

UPP接口

module uPP_ddio(
                    clk,
                    oe,
                    datain,
                    dataout
                    );
input oe;
input clk;
input[31:0]      datain;
output[15:0]      dataout;
reg[15:0]         data_reg;
reg                 state         = 0;

//assign



   dataout   = (oe == 1) ?  data_reg   :  16'd0   ;
assign dataout = data_reg;
always @ (posedge clk)
    begin
        state <= ~state;
        if(state)
            data_reg <= datain[31:16];
        else
            data_reg <= datain[15:0];
    end

endmodule

最后整体图：