Do not panic!
分类: 嵌入式
2015-04-16 10:42:47
原文地址:ARM-Linux时钟初始化 作者:Cheney-Xu
ARM-Linux时钟初始化
ARM-linux时钟初始化是从MACHINE_START中的map_io函数开始的,map_io函数中会调用s3c24xx_init_clocks(12000000);来进行,我们来看一下初始化过程 |
static struct cpu_table *cpu; void __init s3c24xx_init_clocks(int xtal) { if (xtal == 0) xtal = 12*1000*1000;
if (cpu == NULL) panic("s3c24xx_init_clocks: no cpu setup?\n");
if (cpu->init_clocks == NULL) panic("s3c24xx_init_clocks: cpu has no clock init\n"); else (cpu->init_clocks)(xtal); } |
示例如下: |
struct cpu_table { unsigned long idcode; unsigned long idmask; void (*map_io)(void); void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); void (*init_clocks)(int xtal); int (*init)(void); const char *name; }; |
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static struct cpu_table cpu_ids[] __initdata = { //…… { .idcode = 0x32440000, .idmask = 0xffffffff, .map_io = s3c244x_map_io, .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2440_init, .name = name_s3c2440 }, { .idcode = 0x32440001, .idmask = 0xffffffff, .map_io = s3c244x_map_io, .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2440_init, .name = name_s3c2440a }, { .idcode = 0x32440aaa, .idmask = 0xffffffff, .map_io = s3c244x_map_io, .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2442_init, .name = name_s3c2442 }, { .idcode = 0x32440aab, .idmask = 0xffffffff, .map_io = s3c244x_map_io, .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2442_init, .name = name_s3c2442b }, //…… }; |
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void __init s3c244x_init_clocks(int xtal) { /* initialise the clocks here, to allow other things like the * console to use them, and to add new ones after the initialisation */ register_baseclocks(xtal); s3c244x_setup_clocks(); s3c2410_baseclk_add(); } |
s3c24xx_register_baseclocks函数会向系统注册基本时钟,S3C2440A时钟链路:由外晶振OSC(或外部时钟)提供时钟输入,然后分成两路,一路由MPLL锁相环倍频出时钟FCK(核时钟),然后经分频出两路时钟HCLK(AHB总线外设时钟)和PCLK(APB总线外设时钟),另一路由UPLL锁相环倍频出时钟UCLK,为USB外设提供时钟,以下基本时钟中,xtal为外部晶振时钟,clk_mpll为经过MPLL锁相环倍频出时钟,clk_upll为由UPLL锁相环倍频出时钟UCLK,clk_f为内核时钟,即主频,clk_h为HCLK(AHB总线外设时钟)clk_p为PCLK(APB总线外设时钟) |
int __init s3c24xx_register_baseclocks(unsigned long xtal) { printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); clk_xtal.rate = xtal;
/* register our clocks */
if (s3c24xx_register_clock(&clk_xtal) < 0) printk(KERN_ERR "failed to register master xtal\n");
if (s3c24xx_register_clock(&clk_mpll) < 0) printk(KERN_ERR "failed to register mpll clock\n");
if (s3c24xx_register_clock(&clk_upll) < 0) printk(KERN_ERR "failed to register upll clock\n");
if (s3c24xx_register_clock(&clk_f) < 0) printk(KERN_ERR "failed to register cpu fclk\n");
if (s3c24xx_register_clock(&clk_h) < 0) printk(KERN_ERR "failed to register cpu hclk\n");
if (s3c24xx_register_clock(&clk_p) < 0) printk(KERN_ERR "failed to register cpu pclk\n");
return 0; } |
struct clk { struct list_head list; struct module *owner; struct clk *parent; const char *name; int id; int usage; unsigned long rate; unsigned long ctrlbit;
int (*enable)(struct clk *, int enable); int (*set_rate)(struct clk *c, unsigned long rate); unsigned long (*get_rate)(struct clk *c); unsigned long (*round_rate)(struct clk *c, unsigned long rate); int (*set_parent)(struct clk *c, struct clk *parent); }; |
clock.c文件定义一个list_head的链表,s3c24xx_register_clock函数会将clk结 构体的变量加入到这个链表中,函数定义如下 |
static LIST_HEAD(clocks); int s3c24xx_register_clock(struct clk *clk) { if (clk->enable == NULL) clk->enable = clk_null_enable;
/* add to the list of available clocks */ /* Quick check to see if this clock has already been registered. */ BUG_ON(clk->list.prev != clk->list.next);
spin_lock(&clocks_lock); list_add(&clk->list, &clocks); spin_unlock(&clocks_lock);
return 0; } |
各主时钟的定义如下: |
struct clk clk_xtal = { .name = "xtal", .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, };
struct clk clk_ext = { .name = "ext", .id = -1, };
struct clk clk_epll = { .name = "epll", .id = -1, };
struct clk clk_mpll = { .name = "mpll", .id = -1, .set_rate = clk_default_setrate, };
struct clk clk_upll = { .name = "upll", .id = -1, .parent = NULL, .ctrlbit = 0, };
struct clk clk_f = { .name = "fclk", .id = -1, .rate = 0, .parent = &clk_mpll, .ctrlbit = 0, .set_rate = clk_default_setrate, };
struct clk clk_h = { .name = "hclk", .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, .set_rate = clk_default_setrate, };
struct clk clk_p = { .name = "pclk", .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, .set_rate = clk_default_setrate, };
struct clk clk_usb_bus = { .name = "usb-bus", .id = -1, .rate = 0, .parent = &clk_upll, };
struct clk s3c24xx_uclk = { .name = "uclk", .id = -1, };
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时钟注册进系统后便可以通过,内核的API来操作时钟了,struct clk *clk_get(struct device *dev, const char *id)函数来获取一个名为Id的clk结构体指针,然后可以通过clk_get_rate来获取该时钟的频率, 如:printk(KERN_DEBUG ”fclk=%d \n”,clk_get_rate(clk_get(NULL,”fclk”))); s3c244x_setup_clocks(void)会设置系统的基本时钟 |
void __init_or_cpufreq s3c244x_setup_clocks(void) { struct clk *xtal_clk; unsigned long clkdiv; unsigned long camdiv; unsigned long xtal; unsigned long hclk, fclk, pclk; int hdiv = 1;
xtal_clk = clk_get(NULL, "xtal"); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
clkdiv = __raw_readl(S3C2410_CLKDIVN); camdiv = __raw_readl(S3C2440_CAMDIVN);
/* work out clock scalings */
switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { case S3C2440_CLKDIVN_HDIVN_1: hdiv = 1; break;
case S3C2440_CLKDIVN_HDIVN_2: hdiv = 2; break;
case S3C2440_CLKDIVN_HDIVN_4_8: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; break;
case S3C2440_CLKDIVN_HDIVN_3_6: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; break; }
hclk = fclk / hdiv; pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
/* print brief summary of clocks, etc */
printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk); }
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s3c24xx_setup_clocks(fclk, hclk, pclk);它向链表中的相关变量赋值,定义如下: |
void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, unsigned long hclk, unsigned long pclk) { clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), clk_xtal.rate);
clk_mpll.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; clk_f.rate = fclk; } |