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s5pv210 三星u-boot dnw代码分析

分类： 嵌入式

2016-01-17 21:44:25

参考http://www.arm9home.net/read.php?tid-80476.html
http://www.arm9home.net/read.php?tid-25944.html
https://github.com/kangear/tiny210v2-uboot

4412的u-boot:
https://github.com/friendlyarm/uboot_tiny4412

cmd_usbd.c :

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  1. /*
  2.  * common/cmd_usbd.c
  3.  *
  4.  * $Id: cmd_usbd.c,v 1.2 2009/01/28 00:11:42 dark0351 Exp $
  5.  *
  6.  * (C) Copyright 2007
  7.  * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
  8.  *    - support for S3C2412, S3C2443 and S3C6400
  9.  *
  10.  * (C) Copyright SAMSUNG Electronics
  11.  * SW.LEE <hitchcar@samsung.com>
  12.  * - add USB device fo S3C2440A, S3C24A0A
  13.  *
  14.  * (C) Copyright 2000
  15.  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  16.  *
  17.  * See file CREDITS for list of people who contributed to this
  18.  * project.
  19.  *
  20.  * This program is free software; you can redistribute it and/or
  21.  * modify it under the terms of the GNU General Public License as
  22.  * published by the Free Software Foundation; either version 2 of
  23.  * the License, or (at your option) any later version.
  24.  */

  26. /*
  27.  * Memory Functions
  28.  *
  29.  * Copied from FADS ROM, Dan Malek (dmalek@jlc.net)
  30.  */

  32. #include <common.h>
  33. #include <command.h>

  35. #ifdef CONFIG_S3C_USBD

  37. #include <regs.h>

  39. #if defined(CONFIG_S3C2412) || defined(CONFIG_S3C2442)
  40. #include "../cpu/s3c24xx/usbd-fs.h"
  41. #elif defined(CONFIG_S3C2443) || defined(CONFIG_S3C2450) || defined(CONFIG_S3C2416)
  42. #include "../cpu/s3c24xx/usbd-hs.h"
  43. #elif defined(CONFIG_S3C6400) || defined(CONFIG_S3C6410) || defined(CONFIG_S3C6430)
  44. #include "../cpu/s3c64xx/usbd-otg-hs.h"
  45. #elif defined(CONFIG_S5PC100)
  46. #include "../cpu/s5pc1xx/usbd-otg-hs.h"
  47. #elif defined(CONFIG_S5PC110)
  48. #include "../cpu/s5pc11x/usbd-otg-hs.h"
  49. #elif defined(CONFIG_S5P6440)
  50. #include "../cpu/s5p64xx/usbd-otg-hs.h"
  51. #elif defined(CONFIG_S5P6442)
  52. #include "../cpu/s5p644x/usbd-otg-hs.h"
  53. #else
  54. #error "* CFG_ERROR : you have to setup right Samsung CPU configuration"
  55. #endif

  57. #undef    CMD_USBD_DEBUG
  58. #ifdef    CMD_USBD_DEBUG
  59. #define    PRINTF(fmt,args...)    printf (fmt ,##args)
  60. #else
  61. #define PRINTF(fmt,args...)
  62. #endif

  64. static const char pszMe[] = "usbd: ";

  66. int do_usbd_dnw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  67. {

  69.     if (argv[0][0] == 'u') {
  70.         DNW = 0;
  71.     }
  72.     else {
  73.         DNW = 1;
  74.         s3c_got_header = 0;
  75.     }

  77.     switch (argc) {
  78.     case 1 :
  79.         s3c_usbd_dn_addr = USBD_DOWN_ADDR;    /* Default Address */
  80.         break;
  81.     case 2 :
  82.         s3c_usbd_dn_addr = simple_strtoul(argv[1], NULL, 16);
  83.         break;
  84.     default:
  85.         printf ("Usage:\n%s\n", cmdtp->usage);
  86.         return 1;
  87.     }

  89.     s3c_receive_done = 0;

  91.     s3c_usbctl_init(0);
  92.     s3c_usbc_activate();

  94.     PRINTF("Download address 0x%08x\n", s3c_usbd_dn_addr);
  95.     printf("Now, Waiting for DNW to transmit data\n");

  97.     while (1) {
  98.         if (S3C_USBD_DETECT_IRQ()) {
  99.             s3c_udc_int_hndlr();
  100.             S3C_USBD_CLEAR_IRQ();
  101.         }

  103.         if (s3c_receive_done)
  104.             break;

  106.         if (serial_tstc()) {
  107.             serial_getc();
  108.             break;
  109.         }
  110.     }

  112.     /* when operation is done, usbd must be stopped */
  113.     s3c_usb_stop();

  115.     return 0;
  116. }

  118. #if 0 /* ud command not support yet */
  119. U_BOOT_CMD(
  120.     ud, 3, 0, do_usbd_dnw,
  121.     "ud - initialize USB device and ready to receive for LINUX server (specific)\n",
  122.     "[download address]\n"
  123. );
  124. #endif

  126. U_BOOT_CMD(
  127.     dnw, 3, 0, do_usbd_dnw,
  128.     "dnw - initialize USB device and ready to receive for Windows server (specific)\n",
  129.     "[download address]\n"
  130. );

  132. #endif    /* CONFIG_S3C_USBD */
Usbd-otg-hs.c (cpu\s5pc11x)

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  1. /*
  2.  * cpu/s5pc1xx/usbd-otg-hs.c
  3.  *
  4.  * (C) Copyright 2007
  5.  * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
  6.  *    - only support for S5PC100
  7.  *
  8.  * This program is free software; you can redistribute it and/or
  9.  * modify it under the terms of the GNU General Public License as
  10.  * published by the Free Software Foundation; either version 2 of
  11.  * the License, or (at your option) any later version.
  12.  *
  13.  * This program is distributed in the hope that it will be useful,
  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16.  * GNU General Public License for more details.
  17.  *
  18.  * You should have received a copy of the GNU General Public License
  19.  * along with this program; if not, write to the Free Software
  20.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21.  * MA 02111-1307 USA
  22.  */

  24. #include <common.h>

  26. #if defined(CONFIG_S5PC110)
  27. #include <command.h>
  28. #include <asm/errno.h>
  29. #include <asm/io.h>
  30. #include <regs.h>
  31. #include "usbd-otg-hs.h"

  33. #undef USB_OTG_DEBUG_SETUP
  34. #ifdef USB_OTG_DEBUG_SETUP
  35. #define DBG_SETUP0(fmt, args...) printf("[%s:%d] " fmt, __FUNCTION__, __LINE__, ##args)
  36. #define DBG_SETUP1(fmt, args...) printf("\t" fmt, ##args)
  37. #define DBG_SETUP2(fmt, args...) printf(fmt, ##args)
  38. #else
  39. #define DBG_SETUP0(fmt, args...) do { } while (0)
  40. #define DBG_SETUP1(fmt, args...) do { } while (0)
  41. #define DBG_SETUP2(fmt, args...) do { } while (0)
  42. #endif

  44. #undef USB_OTG_DEBUG_BULK
  45. #ifdef USB_OTG_DEBUG_BULK
  46. #define DBG_BULK0(fmt, args...) printf("[%s:%d] " fmt, __FUNCTION__, __LINE__, ##args)
  47. #define DBG_BULK1(fmt, args...)    printf("\t" fmt, ##args)
  48. #else
  49. #define DBG_BULK0(fmt, args...) do { } while (0)
  50. #define DBG_BULK1(fmt, args...) do { } while (0)
  51. #endif

  53. #define USB_CHECKSUM_EN

  55. #define TRUE    1
  56. #define FALSE    0
  57. #define SUSPEND_RESUME_ON FALSE

  59. u32 s3c_usbd_dn_addr = 0;
  60. u32 s3c_usbd_dn_cnt = 0;
  61. u32 remode_wakeup;
  62. u16 config_value;

  64. int DNW;
  65. int s3c_receive_done = 0;
  66. int s3c_got_header = 0;
  67. int s3c_usb_phy_inited=0;
  68. int s3c_usb_connected_status= 0;/*0,none,1,usb connected,2,power connected,3,bad usb connected*/
  69. USB_OPMODE    op_mode = USB_CPU;
  70. USB_SPEED    speed = USB_HIGH;

  72. otg_dev_t    otg;
  73. get_status_t    get_status;
  74. get_intf_t    get_intf;

  76. enum EP_INDEX
  77. {
  78.     EP0, EP1, EP2, EP3, EP4
  79. };

  81. /*------------------------------------------------*/
  82. /* EP0 state */
  83. enum EP0_STATE
  84. {
  85.     EP0_STATE_INIT            = 0,
  86.     EP0_STATE_GD_DEV_0        = 11,
  87.     EP0_STATE_GD_DEV_1        = 12,
  88.     EP0_STATE_GD_DEV_2        = 13,
  89.     EP0_STATE_GD_CFG_0        = 21,
  90.     EP0_STATE_GD_CFG_1        = 22,
  91.     EP0_STATE_GD_CFG_2        = 23,
  92.     EP0_STATE_GD_CFG_3        = 24,
  93.     EP0_STATE_GD_CFG_4        = 25,
  94.     EP0_STATE_GD_STR_I0        = 30,
  95.     EP0_STATE_GD_STR_I1        = 31,
  96.     EP0_STATE_GD_STR_I2        = 32,
  97.     EP0_STATE_GD_DEV_QUALIFIER    = 33,
  98.     EP0_STATE_INTERFACE_GET        = 34,
  99.     EP0_STATE_GET_STATUS0        = 35,
  100.     EP0_STATE_GET_STATUS1        = 36,
  101.     EP0_STATE_GET_STATUS2        = 37,
  102.     EP0_STATE_GET_STATUS3        = 38,
  103.     EP0_STATE_GET_STATUS4        = 39,
  104.     EP0_STATE_GD_OTHER_SPEED    = 40,
  105.     EP0_STATE_GD_CFG_ONLY_0     = 41,
  106.     EP0_STATE_GD_CFG_ONLY_1     = 42,
  107.     EP0_STATE_GD_IF_ONLY_0        = 44,
  108.     EP0_STATE_GD_IF_ONLY_1        = 45,
  109.     EP0_STATE_GD_EP0_ONLY_0     = 46,
  110.     EP0_STATE_GD_EP1_ONLY_0     = 47,
  111.     EP0_STATE_GD_EP2_ONLY_0     = 48,
  112.     EP0_STATE_GD_EP3_ONLY_0     = 49,
  113.     EP0_STATE_GD_OTHER_SPEED_HIGH_1    = 51,
  114.     EP0_STATE_GD_OTHER_SPEED_HIGH_2    = 52,
  115.     EP0_STATE_GD_OTHER_SPEED_HIGH_3    = 53
  116. };

  118. /*definitions related to CSR setting */

  120. /* S5P_OTG_GOTGCTL*/
  121. #define B_SESSION_VALID        (0x1<<19)
  122. #define A_SESSION_VALID        (0x1<<18)

  124. /* S5P_OTG_GAHBCFG*/
  125. #define PTXFE_HALF        (0<<8)
  126. #define PTXFE_ZERO        (1<<8)
  127. #define NPTXFE_HALF        (0<<7)
  128. #define NPTXFE_ZERO        (1<<7)
  129. #define MODE_SLAVE        (0<<5)
  130. #define MODE_DMA        (1<<5)
  131. #define BURST_SINGLE        (0<<1)
  132. #define BURST_INCR        (1<<1)
  133. #define BURST_INCR4        (3<<1)
  134. #define BURST_INCR8        (5<<1)
  135. #define BURST_INCR16        (7<<1)
  136. #define GBL_INT_UNMASK        (1<<0)
  137. #define GBL_INT_MASK        (0<<0)

  139. /* S5P_OTG_GRSTCTL*/
  140. #define AHB_MASTER_IDLE        (1u<<31)
  141. #define CORE_SOFT_RESET        (0x1<<0)

  143. /* S5P_OTG_GINTSTS/S5P_OTG_GINTMSK core interrupt register */
  144. #define INT_RESUME        (1u<<31)
  145. #define INT_DISCONN        (0x1<<29)
  146. #define INT_CONN_ID_STS_CNG    (0x1<<28)
  147. #define INT_OUT_EP        (0x1<<19)
  148. #define INT_IN_EP        (0x1<<18)
  149. #define INT_ENUMDONE        (0x1<<13)
  150. #define INT_RESET        (0x1<<12)
  151. #define INT_SUSPEND        (0x1<<11)
  152. #define INT_TX_FIFO_EMPTY    (0x1<<5)
  153. #define INT_RX_FIFO_NOT_EMPTY    (0x1<<4)
  154. #define INT_SOF            (0x1<<3)
  155. #define INT_DEV_MODE        (0x0<<0)
  156. #define INT_HOST_MODE        (0x1<<1)

  158. /* S5P_OTG_GRXSTSP STATUS*/
  159. #define GLOBAL_OUT_NAK            (0x1<<17)
  160. #define OUT_PKT_RECEIVED        (0x2<<17)
  161. #define OUT_TRNASFER_COMPLETED        (0x3<<17)
  162. #define SETUP_TRANSACTION_COMPLETED    (0x4<<17)
  163. #define SETUP_PKT_RECEIVED        (0x6<<17)

  165. /* S5P_OTG_DCTL device control register */
  166. #define NORMAL_OPERATION        (0x1<<0)
  167. #define SOFT_DISCONNECT            (0x1<<1)
  168. #define    TEST_J_MODE            (TEST_J<<4)
  169. #define    TEST_K_MODE            (TEST_K<<4)
  170. #define    TEST_SE0_NAK_MODE        (TEST_SE0_NAK<<4)
  171. #define    TEST_PACKET_MODE        (TEST_PACKET<<4)
  172. #define    TEST_FORCE_ENABLE_MODE        (TEST_FORCE_ENABLE<<4)
  173. #define TEST_CONTROL_FIELD        (0x7<<4)

  175. /* S5P_OTG_DAINT device all endpoint interrupt register */
  176. #define INT_IN_EP0            (0x1<<0)
  177. #define INT_IN_EP1            (0x1<<1)
  178. #define INT_IN_EP3            (0x1<<3)
  179. #define INT_OUT_EP0            (0x1<<16)
  180. #define INT_OUT_EP2            (0x1<<18)
  181. #define INT_OUT_EP4            (0x1<<20)

  183. /* S5P_OTG_DIEPCTL0/S5P_OTG_DOEPCTL0 */
  184. #define DEPCTL_EPENA            (0x1<<31)
  185. #define DEPCTL_EPDIS            (0x1<<30)
  186. #define DEPCTL_SNAK            (0x1<<27)
  187. #define DEPCTL_CNAK            (0x1<<26)
  188. #define DEPCTL_CTRL_TYPE        (EP_TYPE_CONTROL<<18)
  189. #define DEPCTL_ISO_TYPE            (EP_TYPE_ISOCHRONOUS<<18)
  190. #define DEPCTL_BULK_TYPE        (EP_TYPE_BULK<<18)
  191. #define DEPCTL_INTR_TYPE        (EP_TYPE_INTERRUPT<<18)
  192. #define DEPCTL_USBACTEP            (0x1<<15)

  194. /*ep0 enable, clear nak, next ep0, max 64byte */
  195. #define EPEN_CNAK_EP0_64 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(0<<0))

  197. /*ep0 enable, clear nak, next ep0, 8byte */
  198. #define EPEN_CNAK_EP0_8 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(3<<0))

  200. /* DIEPCTLn/DOEPCTLn */
  201. #define BACK2BACK_SETUP_RECEIVED    (0x1<<6)
  202. #define INTKN_TXFEMP            (0x1<<4)
  203. #define NON_ISO_IN_EP_TIMEOUT        (0x1<<3)
  204. #define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
  205. #define AHB_ERROR            (0x1<<2)
  206. #define TRANSFER_DONE            (0x1<<0)


  209. /* codes representing languages */
  210. const u8 string_desc0[] =
  211. {
  212.     4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H,
  213. };

  215. const u8 string_desc1[] = /* Manufacturer */
  216. {
  217.     (0x14+2), STRING_DESCRIPTOR,
  218.     'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0,
  219.     'm', 0x0, ' ', 0x0, 'M', 0x0, 'C', 0x0, 'U', 0x0,
  220. };

  222. const u8 string_desc2[] = /* Product */
  223. {
  224.     (0x2a+2), STRING_DESCRIPTOR,
  225.     'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0,
  226.     '3', 0x0, 'C', 0x0, '6', 0x0, '4', 0x0, '0', 0x0,
  227.     '0', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0,
  228.     's', 0x0, 't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0,
  229.     'D', 0x0
  230. };

  232. /* setting the device qualifier descriptor and a string descriptor */
  233. const u8 qualifier_desc[] =
  234. {
  235.     0x0a,    /* 0 desc size */
  236.     0x06,    /* 1 desc type (DEVICE_QUALIFIER)*/
  237.     0x00,    /* 2 USB release */
  238.     0x02,    /* 3 => 2.00*/
  239.     0xFF,    /* 4 class */
  240.     0x00,    /* 5 subclass */
  241.     0x00,    /* 6 protocol */
  242.     64,    /* 7 max pack size */
  243.     0x01,    /* 8 number of other-speed configuration */
  244.     0x00,    /* 9 reserved */
  245. };

  247. const u8 config_full[] =
  248. {
  249.     0x09,    /* 0 desc size */
  250.     0x07,    /* 1 desc type (other speed)*/
  251.     0x20,    /* 2 Total length of data returned */
  252.     0x00,    /* 3 */
  253.     0x01,    /* 4 Number of interfaces supported by this speed configuration */
  254.     0x01,    /* 5 value to use to select configuration */
  255.     0x00,    /* 6 index of string desc */
  256.         /* 7 same as configuration desc */
  257.     CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED,
  258.     0x19,    /* 8 same as configuration desc */

  260. };

  262. const u8 config_full_total[] =
  263. {
  264.   0x09, 0x07 ,0x20 ,0x00 ,0x01 ,0x01 ,0x00 ,0xC0 ,0x19,
  265.   0x09 ,0x04 ,0x00 ,0x00 ,0x02 ,0xff ,0x00 ,0x00 ,0x00,
  266.   0x07 ,0x05 ,0x83 ,0x02 ,0x40 ,0x00 ,0x00,
  267.   0x07 ,0x05 ,0x04 ,0x02 ,0x40 ,0x00 ,0x00
  268. };

  270. const u8 config_high[] =
  271. {
  272.     0x09,    /* 0 desc size */
  273.     0x07,    /* 1 desc type (other speed)*/
  274.     0x20,    /* 2 Total length of data returned */
  275.     0x00,    /* 3 */
  276.     0x01,    /* 4 Number of interfaces supported by this speed configuration */
  277.     0x01,    /* 5 value to use to select configuration */
  278.     0x00,    /* 6 index of string desc */
  279.         /* 7 same as configuration desc */
  280.     CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED,
  281.     0x19,    /* 8 same as configuration desc */

  283. };

  285. const u8 config_high_total[] =
  286. {
  287.   0x09, 0x07 ,0x20 ,0x00 ,0x01 ,0x01 ,0x00 ,0xC0 ,0x19,
  288.   0x09 ,0x04 ,0x00 ,0x00 ,0x02 ,0xff ,0x00 ,0x00 ,0x00,
  289.   0x07 ,0x05 ,0x81 ,0x02 ,0x00 ,0x02 ,0x00,
  290.   0x07 ,0x05 ,0x02 ,0x02 ,0x00 ,0x02 ,0x00
  291. };

  293. /* Descriptor size */
  294. enum DESCRIPTOR_SIZE
  295. {
  296.     DEVICE_DESC_SIZE    = sizeof(device_desc_t),
  297.     STRING_DESC0_SIZE    = sizeof(string_desc0),
  298.     STRING_DESC1_SIZE    = sizeof(string_desc1),
  299.     STRING_DESC2_SIZE    = sizeof(string_desc2),
  300.     CONFIG_DESC_SIZE    = sizeof(config_desc_t),
  301.     INTERFACE_DESC_SIZE    = sizeof(intf_desc_t),
  302.     ENDPOINT_DESC_SIZE    = sizeof(ep_desc_t),
  303.     DEVICE_QUALIFIER_SIZE    = sizeof(qualifier_desc),
  304.     OTHER_SPEED_CFG_SIZE    = 9

  306. };

  308. /*32 <cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>*/
  309. #define CONFIG_DESC_TOTAL_SIZE    \
  310.     (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2)
  311. #define TEST_PKT_SIZE 53

  313. u8 test_pkt [TEST_PKT_SIZE] = {
  314.     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,    /*JKJKJKJK x 9*/
  315.     0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,    /*JJKKJJKK x 8*/
  316.     0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,    /*JJJJKKKK x 8*/
  317.     0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,    /*JJJJJJJKKKKKKK x8 - '1'*/
  318.     0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,        /*'1' + JJJJJJJK x 8*/
  319.     0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E    /*{JKKKKKKK x 10},JK*/
  320. };

  322. void s3c_usb_init_phy(void)
  323. {
  324.     writel(readl(USB_PHY_CONTROL)|(1<<0), USB_PHY_CONTROL);    /*USB PHY0 Enable */
  325.     
  326.     writel(0xa0, S5P_OTG_PHYPWR);
  327.     writel(0x3, S5P_OTG_PHYCLK);
  328.     writel(0x1, S5P_OTG_RSTCON);
  329.     udelay(10);
  330.     writel(0x0, S5P_OTG_RSTCON);
  331.     udelay(10);

  333. }

  335. /* OTG PHY Power Off */
  336. void s3c_usb_phy_off(void) {
  337.     writel(readl(S5P_OTG_PHYPWR)|(0x18), S5P_OTG_PHYPWR);
  338.     writel(readl(USB_PHY_CONTROL)&~(1<<0), USB_PHY_CONTROL);
  339.     s3c_usb_phy_inited=0;
  340. }

  342. void s3c_usb_core_soft_reset(void)
  343. {
  344.     u32 tmp;

  346.     writel(CORE_SOFT_RESET, S5P_OTG_GRSTCTL);

  348.     do
  349.     {
  350.         tmp = readl(S5P_OTG_GRSTCTL);
  351.     }while(!(tmp & AHB_MASTER_IDLE));

  353. }

  355. void s3c_usb_wait_cable_insert(void)
  356. {
  357.     u32 tmp;
  358.     int ucFirst=1;

  360.     do {
  361.         udelay(50);

  363.         tmp = readl(S5P_OTG_GOTGCTL);

  365.         if (tmp & (B_SESSION_VALID|A_SESSION_VALID)) {
  366.             printf("OTG cable Connected!\n");
  367.             break;
  368.         } else if(ucFirst == 1) {
  369.             printf("Insert a OTG cable into the connector!\n");
  370.             ucFirst = 0;
  371.         }
  372.     } while(1);
  373. }

  375. void s3c_usb_init_core(void)
  376. {
  377.     writel(PTXFE_HALF|NPTXFE_HALF|MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK,
  378.         S5P_OTG_GAHBCFG);

  380.     writel( 0<<15        /* PHY Low Power Clock sel */
  381.         |1<<14        /* Non-Periodic TxFIFO Rewind Enable */
  382.         |0x5<<10    /* Turnaround time */
  383.         |0<<9        /* 0:HNP disable, 1:HNP enable */
  384.         |0<<8        /* 0:SRP disable, 1:SRP enable */
  385.         |0<<7        /* ULPI DDR sel */
  386.         |0<<6        /* 0: high speed utmi+, 1: full speed serial */
  387.         |0<<4        /* 0: utmi+, 1:ulpi */
  388.         |1<<3        /* phy i/f 0:8bit, 1:16bit */
  389.         |0x7<<0,    /* HS/FS Timeout**/
  390.         S5P_OTG_GUSBCFG );
  391. }

  393. void s3c_usb_check_current_mode(u8 *pucMode)
  394. {
  395.     u32 tmp;

  397.     tmp = readl(S5P_OTG_GINTSTS);
  398.     *pucMode = tmp & 0x1;
  399. }

  401. void s3c_usb_set_soft_disconnect(void)
  402. {
  403.     u32 tmp;

  405.     tmp = readl(S5P_OTG_DCTL);
  406.     tmp |= SOFT_DISCONNECT;
  407.     writel(tmp, S5P_OTG_DCTL);
  408. }

  410. void s3c_usb_clear_soft_disconnect(void)
  411. {
  412.     u32 tmp;

  414.     tmp = readl(S5P_OTG_DCTL);
  415.     tmp &= ~SOFT_DISCONNECT;
  416.     writel(tmp, S5P_OTG_DCTL);
  417. }

  419. void s3c_usb_init_device(void)
  420. {
  421.     writel(1<<18|otg.speed<<0, S5P_OTG_DCFG); /* [][1: full speed(30Mhz) 0:high speed]*/

  423.     writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  424.         INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY,
  425.         S5P_OTG_GINTMSK);    /*gint unmask */
  426.     s3c_usb_phy_inited=1;
  427. }

  429. int s3c_usbctl_init(int ischeckstatus)/*diog, if not for check status, donot need wait cable insert*/
  430. {
  431.     u8 ucMode;

  433.     DBG_SETUP0("USB Control Init\n");
  434.     
  435.     otg.speed = speed;
  436.     otg.set_config = 0;
  437.     otg.ep0_state = EP0_STATE_INIT;
  438.     otg.ep0_substate = 0;
  439.     s3c_usb_init_phy();
  440.     s3c_usb_core_soft_reset();
  441.     if(!ischeckstatus)
  442.     s3c_usb_wait_cable_insert();
  443.     s3c_usb_init_core();
  444.     s3c_usb_check_current_mode(&ucMode);

  446.     if (ucMode == INT_DEV_MODE) {
  447.         s3c_usb_set_soft_disconnect();
  448.         udelay(10);
  449.         s3c_usb_clear_soft_disconnect();
  450.         s3c_usb_init_device();
  451.         return 0;
  452.     } else {
  453.         printf("Error : Current Mode is Host\n");
  454.         return 0;
  455.     }
  456. }

  458. int s3c_usbc_activate (void)
  459. {
  460.     /* dont used in usb high speed, but used in common file cmd_usbd.c */
  461.     return 0;
  462. }

  464. int s3c_usb_stop (void)
  465. {
  466.     /* dont used in usb high speed, but used in common file cmd_usbd.c */
  467.     s3c_usb_core_soft_reset();
  468.     s3c_usb_phy_off();
  469.     return 0;
  470. }

  472. void s3c_usb_print_pkt(u8 *pt, u8 count)
  473. {
  474.     int i;
  475.     printf("[s3c_usb_print_pkt:");

  477.     for(i=0;i<count;i++)
  478.         printf("%x,", pt[i]);

  480.     printf("]\n");
  481. }

  483. void s3c_usb_verify_checksum(void)
  484. {
  485.     u8 *cs_start, *cs_end;
  486.     u16 dnCS;
  487.     u16 checkSum;

  489.     printf("Checksum is being calculated.");

  491.     /* checksum calculation */
  492.     cs_start = (u8*)otg.dn_addr;
  493.     cs_end = (u8*)(otg.dn_addr+otg.dn_filesize-10);
  494.     checkSum = 0;
  495.     while(cs_start < cs_end) {
  496.         checkSum += *cs_start++;
  497.         if(((u32)cs_start&0xfffff)==0) printf(".");
  498.     }

  500.     /* fixed alignment fault in case when cs_end is odd. */
  501.     dnCS = (u16)((cs_end[1]<<8) + cs_end[0]);
  502.     //dnCS = *(u16 *)cs_end;

  504.     if (checkSum == dnCS)
  505.     {
  506.         printf("\nChecksum O.K.\n");
  507.     }
  508.     else
  509.     {
  510.         printf("\nChecksum Value => MEM:%x DNW:%x\n",checkSum,dnCS);
  511.         printf("Checksum failed.\n\n");
  512.     }

  514. }

  516. void s3c_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
  517. {
  518.     if(type == EP_TYPE_CONTROL)
  519.     {
  520.         writel((pktcnt<<19)|(xfersize<<0), S5P_OTG_DIEPTSIZ0);
  521.     }
  522.     else if(type == EP_TYPE_BULK)
  523.     {
  524.         writel((1<<29)|(pktcnt<<19)|(xfersize<<0), S5P_OTG_DIEPTSIZ_IN);
  525.     }
  526. }

  528. void s3c_usb_set_outep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
  529. {
  530.     if(type == EP_TYPE_CONTROL)
  531.     {
  532.         writel((1<<29)|(pktcnt<<19)|(xfersize<<0), S5P_OTG_DOEPTSIZ0);
  533.     }
  534.     else if(type == EP_TYPE_BULK)
  535.     {
  536.         writel((pktcnt<<19)|(xfersize<<0), S5P_OTG_DOEPTSIZ_OUT);
  537.     }
  538. }

  540. void s3c_usb_write_ep0_fifo(u8 *buf, int num)
  541. {
  542.     int i;
  543.     u32 Wr_Data=0;

  545.     DBG_SETUP1("[s3c_usb_write_ep0_fifo:");

  547.     for(i=0;i<num;i+=4)
  548.     {
  549.         Wr_Data = ((*(buf+3))<<24)|((*(buf+2))<<16)|((*(buf+1))<<8)|*buf;
  550.         DBG_SETUP2(" 0x%08x,", Wr_Data);
  551.         writel(Wr_Data, S5P_OTG_EP0_FIFO);
  552.         buf += 4;
  553.     }

  555.     DBG_SETUP2("]\n");
  556. }


  559. void s3c_usb_write_in_fifo(u8 *buf, int num)
  560. {
  561.     int i;
  562.     u32 data=0;

  564.     for(i=0;i<num;i+=4)
  565.     {
  566.         data=((*(buf+3))<<24)|((*(buf+2))<<16)|((*(buf+1))<<8)|*buf;
  567.         writel(data, S5P_OTG_IN_FIFO);
  568.         buf += 4;
  569.     }
  570. }

  572. void s3c_usb_read_out_fifo(u8 *buf, int num)
  573. {
  574.     int i;
  575.     u32 data;

  577.     for (i=0;i<num;i+=4)
  578.     {
  579.         data = readl(S5P_OTG_OUT_FIFO);

  581.         buf[i] = (u8)data;
  582.         buf[i+1] = (u8)(data>>8);
  583.         buf[i+2] = (u8)(data>>16);
  584.         buf[i+3] = (u8)(data>>24);
  585.     }
  586. }

  588. void s3c_usb_get_desc(void)
  589. {
  590.     switch (otg.dev_req.wValue_H) {
  591.     case DEVICE_DESCRIPTOR:
  592.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  593.             otg.dev_req.wLength_L);
  594.         DBG_SETUP1("DEVICE_DESCRIPTOR = 0x%x \n",otg.req_length);
  595.         otg.ep0_state = EP0_STATE_GD_DEV_0;
  596.         break;

  598.     case CONFIGURATION_DESCRIPTOR:
  599.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  600.             otg.dev_req.wLength_L);
  601.         DBG_SETUP1("CONFIGURATION_DESCRIPTOR = 0x%x \n",otg.req_length);

  603.         /* GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 */
  604.         if (otg.req_length > CONFIG_DESC_SIZE){
  605.             otg.ep0_state = EP0_STATE_GD_CFG_0;
  606.         } else
  607.             otg.ep0_state = EP0_STATE_GD_CFG_ONLY_0;
  608.         break;

  610.     case STRING_DESCRIPTOR :
  611.         DBG_SETUP1("STRING_DESCRIPTOR \n");

  613.         switch(otg.dev_req.wValue_L) {
  614.         case 0:
  615.             otg.ep0_state = EP0_STATE_GD_STR_I0;
  616.             break;
  617.         case 1:
  618.             otg.ep0_state = EP0_STATE_GD_STR_I1;
  619.             break;
  620.         case 2:
  621.             otg.ep0_state = EP0_STATE_GD_STR_I2;
  622.             break;
  623.         default:
  624.             break;
  625.         }
  626.         break;

  628.     case ENDPOINT_DESCRIPTOR:
  629.         DBG_SETUP1("ENDPOINT_DESCRIPTOR \n");
  630.         switch(otg.dev_req.wValue_L&0xf) {
  631.         case 0:
  632.             otg.ep0_state=EP0_STATE_GD_EP0_ONLY_0;
  633.             break;
  634.         case 1:
  635.             otg.ep0_state=EP0_STATE_GD_EP1_ONLY_0;
  636.             break;
  637.         default:
  638.             break;
  639.         }
  640.         break;

  642.     case DEVICE_QUALIFIER:
  643.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  644.             otg.dev_req.wLength_L);
  645.         DBG_SETUP1("DEVICE_QUALIFIER = 0x%x \n",otg.req_length);
  646.         otg.ep0_state = EP0_STATE_GD_DEV_QUALIFIER;
  647.         break;

  649.     case OTHER_SPEED_CONFIGURATION :
  650.         DBG_SETUP1("OTHER_SPEED_CONFIGURATION \n");
  651.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  652.             otg.dev_req.wLength_L);
  653.         otg.ep0_state = EP0_STATE_GD_OTHER_SPEED;
  654.         break;

  656.     }
  657. }

  659. void s3c_usb_clear_feature(void)
  660. {
  661.     switch (otg.dev_req.bmRequestType) {
  662.     case DEVICE_RECIPIENT:
  663.         DBG_SETUP1("DEVICE_RECIPIENT \n");
  664.         if (otg.dev_req.wValue_L == 1)
  665.             remode_wakeup = FALSE;
  666.         break;

  668.     case ENDPOINT_RECIPIENT:
  669.         DBG_SETUP1("ENDPOINT_RECIPIENT \n");
  670.         if (otg.dev_req.wValue_L == 0) {
  671.             if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
  672.                 get_status.ep_ctrl= 0;

  674.             /* IN    Endpoint */
  675.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
  676.                 get_status.ep_in= 0;

  678.             /* OUT Endpoint */
  679.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
  680.                 get_status.ep_out= 0;
  681.         }
  682.         break;

  684.     default:
  685.         DBG_SETUP1("\n");
  686.         break;
  687.     }
  688.     otg.ep0_state = EP0_STATE_INIT;

  690. }

  692. void s3c_usb_set_feature(void)
  693. {
  694.     u32 tmp;

  696.     switch (otg.dev_req.bmRequestType) {
  697.     case DEVICE_RECIPIENT:
  698.         DBG_SETUP1("DEVICE_RECIPIENT \n");
  699.         if (otg.dev_req.wValue_L == 1)
  700.             remode_wakeup = TRUE;
  701.             break;

  703.     case ENDPOINT_RECIPIENT:
  704.         DBG_SETUP1("ENDPOINT_RECIPIENT \n");
  705.         if (otg.dev_req.wValue_L == 0) {
  706.             if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
  707.                 get_status.ep_ctrl= 1;

  709.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
  710.                 get_status.ep_in= 1;

  712.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
  713.                 get_status.ep_out= 1;
  714.         }
  715.         break;

  717.     default:
  718.         DBG_SETUP1("\n");
  719.         break;
  720.     }

  722.     switch (otg.dev_req.wValue_L) {
  723.     case EP_STALL:
  724.         /* TBD: additional processing if required */
  725.         break;

  727.     case TEST_MODE:
  728.         if ((0 != otg.dev_req.wIndex_L ) ||(0 != otg.dev_req.bmRequestType))
  729.             break;

  731.         /* Set TEST MODE*/
  732.         tmp = readl(S5P_OTG_DCTL);
  733.         tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_FORCE_ENABLE_MODE);
  734.         writel(tmp, S5P_OTG_DCTL);

  736.         switch(otg.dev_req.wIndex_H) {
  737.         case TEST_J:
  738.             /*Set Test J*/
  739.             tmp = readl(S5P_OTG_DCTL);
  740.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_J_MODE);
  741.             writel(tmp, S5P_OTG_DCTL);
  742.             break;

  744.         case TEST_K:
  745.             /*Set Test K*/
  746.             tmp = readl(S5P_OTG_DCTL);
  747.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_K_MODE);
  748.             writel(tmp, S5P_OTG_DCTL);
  749.             break;

  751.         case TEST_SE0_NAK:
  752.             /*Set Test SE0NAK*/
  753.             tmp = readl(S5P_OTG_DCTL);
  754.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_SE0_NAK_MODE);
  755.             writel(tmp, S5P_OTG_DCTL);
  756.             break;

  758.         case TEST_PACKET:
  759.             DBG_SETUP1 ("Test_packet\n");
  760.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  761.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, TEST_PKT_SIZE);
  762.             s3c_usb_write_ep0_fifo(test_pkt, TEST_PKT_SIZE);
  763.             tmp = readl(S5P_OTG_DCTL);
  764.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_PACKET_MODE);
  765.             writel(tmp, S5P_OTG_DCTL);
  766.             DBG_SETUP1 ("S5P_OTG_DCTL=0x%08x\n", tmp);
  767.             break;
  768.         }
  769.         break;

  771.     default:
  772.         break;
  773.     }
  774.     otg.ep0_state = EP0_STATE_INIT;

  776. }

  778. void s3c_usb_get_status(void)
  779. {
  780.     switch(otg.dev_req.bmRequestType) {
  781.     case (0x80):    /*device */
  782.         DBG_SETUP1("DEVICE\n");
  783.         get_status.Device=((u8)remode_wakeup<<1)|0x1; /* SelfPowered */
  784.         otg.ep0_state = EP0_STATE_GET_STATUS0;
  785.         break;

  787.     case (0x81):    /*interface */
  788.         DBG_SETUP1("INTERFACE\n");
  789.         get_status.Interface=0;
  790.         otg.ep0_state = EP0_STATE_GET_STATUS1;
  791.         break;

  793.     case (0x82):    /*endpoint */
  794.         DBG_SETUP1("ENDPOINT\n");
  795.         if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
  796.             otg.ep0_state = EP0_STATE_GET_STATUS2;

  798.         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
  799.             otg.ep0_state = EP0_STATE_GET_STATUS3;

  801.         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
  802.             otg.ep0_state = EP0_STATE_GET_STATUS4;
  803.         break;

  805.     default:
  806.         DBG_SETUP1("\n");
  807.         break;
  808.     }

  810. }

  812. void s3c_usb_ep0_int_hndlr(void)
  813. {
  814.     u16 i;
  815.     u32 buf[2]={0x0000, };
  816.     u16 addr;

  818.     DBG_SETUP0("Event EP0\n");

  820.     if (otg.ep0_state == EP0_STATE_INIT) {

  822.         for(i=0;i<2;i++)
  823.             buf[i] = readl(S5P_OTG_EP0_FIFO);

  825.         otg.dev_req.bmRequestType = buf[0];
  826.         otg.dev_req.bRequest    = buf[0]>>8;
  827.         otg.dev_req.wValue_L    = buf[0]>>16;
  828.         otg.dev_req.wValue_H    = buf[0]>>24;
  829.         otg.dev_req.wIndex_L    = buf[1];
  830.         otg.dev_req.wIndex_H    = buf[1]>>8;
  831.         otg.dev_req.wLength_L    = buf[1]>>16;
  832.         otg.dev_req.wLength_H    = buf[1]>>24;

  834. #ifdef USB_OTG_DEBUG_SETUP
  835.         s3c_usb_print_pkt((u8 *)&otg.dev_req, 8);
  836. #endif

  838.         switch (otg.dev_req.bRequest) {
  839.         case STANDARD_SET_ADDRESS:
  840.             /* Set Address Update bit */
  841.             addr = (otg.dev_req.wValue_L);
  842.             writel(1<<18|addr<<4|otg.speed<<0, S5P_OTG_DCFG);
  843.             DBG_SETUP1("S5P_OTG_DCFG : %x, STANDARD_SET_ADDRESS : %d\n",
  844.                     readl(S5P_OTG_DCFG), addr);
  845.             otg.ep0_state = EP0_STATE_INIT;
  846.             break;

  848.         case STANDARD_SET_DESCRIPTOR:
  849.             DBG_SETUP1("STANDARD_SET_DESCRIPTOR \n");
  850.             break;

  852.         case STANDARD_SET_CONFIGURATION:
  853.             DBG_SETUP1("STANDARD_SET_CONFIGURATION \n");
  854.             /* Configuration value in configuration descriptor */
  855.             config_value = otg.dev_req.wValue_L;
  856.             otg.set_config = 1;
  857.             otg.ep0_state = EP0_STATE_INIT;
  858.             break;

  860.         case STANDARD_GET_CONFIGURATION:
  861.             DBG_SETUP1("STANDARD_GET_CONFIGURATION \n");
  862.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);

  864.             /*ep0 enable, clear nak, next ep0, 8byte */
  865.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  866.             writel(config_value, S5P_OTG_EP0_FIFO);
  867.             otg.ep0_state = EP0_STATE_INIT;
  868.             break;

  870.         case STANDARD_GET_DESCRIPTOR:
  871.             DBG_SETUP1("STANDARD_GET_DESCRIPTOR :");
  872.             s3c_usb_get_desc();
  873.             break;

  875.         case STANDARD_CLEAR_FEATURE:
  876.             DBG_SETUP1("STANDARD_CLEAR_FEATURE :");
  877.             s3c_usb_clear_feature();
  878.             break;

  880.         case STANDARD_SET_FEATURE:
  881.             DBG_SETUP1("STANDARD_SET_FEATURE :");
  882.             s3c_usb_set_feature();
  883.             break;

  885.         case STANDARD_GET_STATUS:
  886.             DBG_SETUP1("STANDARD_GET_STATUS :");
  887.             s3c_usb_get_status();
  888.             break;

  890.         case STANDARD_GET_INTERFACE:
  891.             DBG_SETUP1("STANDARD_GET_INTERFACE \n");
  892.             otg.ep0_state = EP0_STATE_INTERFACE_GET;
  893.             break;

  895.         case STANDARD_SET_INTERFACE:
  896.             DBG_SETUP1("STANDARD_SET_INTERFACE \n");
  897.             get_intf.AlternateSetting= otg.dev_req.wValue_L;
  898.             otg.ep0_state = EP0_STATE_INIT;
  899.             break;

  901.         case STANDARD_SYNCH_FRAME:
  902.             DBG_SETUP1("STANDARD_SYNCH_FRAME \n");
  903.             otg.ep0_state = EP0_STATE_INIT;
  904.             break;

  906.         default:
  907.             break;
  908.         }
  909.     }

  911.     s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.ctrl_max_pktsize);

  913.     if(otg.speed == USB_HIGH) {
  914.         /*clear nak, next ep0, 64byte */
  915.         writel(((1<<26)|(CONTROL_EP<<11)|(0<<0)), S5P_OTG_DIEPCTL0);
  916.     }
  917.     else {
  918.         /*clear nak, next ep0, 8byte */
  919.         writel(((1<<26)|(CONTROL_EP<<11)|(3<<0)), S5P_OTG_DIEPCTL0);
  920.     }

  922. }

  924. void s3c_usb_set_otherspeed_conf_desc(u32 length)
  925. {
  926.     /* Standard device descriptor */
  927.     if (otg.speed == USB_HIGH)
  928.     {
  929.      if (length ==9)
  930.      {
  931.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 9);
  932.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  933.             s3c_usb_write_ep0_fifo(((u8 *)&config_full)+0, 9);
  934.         }
  935.      else if(length ==32)
  936.         {
  937.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 32);
  938.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  939.             s3c_usb_write_ep0_fifo(((u8 *)&config_full_total)+0, 32);

  941.      }
  942.         otg.ep0_state = EP0_STATE_INIT;
  943.     }
  944.     else
  945.     {
  946.      if (length ==9)
  947.      {
  948.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  949.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  950.             s3c_usb_write_ep0_fifo(((u8 *)&config_high)+0, 8);
  951.         }
  952.      else if(length ==32)
  953.         {
  954.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  955.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  956.             s3c_usb_write_ep0_fifo(((u8 *)&config_high_total)+0, 8);
  957.      }
  958.         otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_1;
  959.     }
  960. }

  962. void s3c_usb_transfer_ep0(void)
  963. {

  965.     DBG_SETUP0("otg.ep0_state = %d\n", otg.ep0_state);

  967.     switch (otg.ep0_state) {
  968.     case EP0_STATE_INIT:
  969.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 0);

  971.         /*ep0 enable, clear nak, next ep0, 8byte */
  972.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  973.         DBG_SETUP1("EP0_STATE_INIT\n");
  974.         break;

  976.     /* GET_DESCRIPTOR:DEVICE */
  977.     case EP0_STATE_GD_DEV_0:
  978.         DBG_SETUP1("EP0_STATE_GD_DEV_0 :");
  979.         if (otg.speed == USB_HIGH) {
  980.             DBG_SETUP1("High Speed\n");

  982.             /*ep0 enable, clear nak, next ep0, max 64byte */
  983.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  984.             if (otg.req_length < DEVICE_DESC_SIZE) {
  985.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  986.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, otg.req_length);
  987.             } else {
  988.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, DEVICE_DESC_SIZE);
  989.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, DEVICE_DESC_SIZE);
  990.             }
  991.             otg.ep0_state = EP0_STATE_INIT;
  992.         } else {
  993.             DBG_SETUP1("Full Speed\n");
  994.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  995.             if(otg.req_length<DEVICE_DESC_SIZE) {
  996.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  997.             } else {
  998.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, DEVICE_DESC_SIZE);
  999.             }

  1001.             if(otg.req_length<FS_CTRL_PKT_SIZE) {
  1002.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, otg.req_length);
  1003.                 otg.ep0_state = EP0_STATE_INIT;
  1004.             } else {
  1005.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, FS_CTRL_PKT_SIZE);
  1006.                 otg.ep0_state = EP0_STATE_GD_DEV_1;
  1007.             }
  1008.         }
  1009.         break;

  1011.     case EP0_STATE_GD_DEV_1:
  1012.         DBG_SETUP1("EP0_STATE_GD_DEV_1\n");
  1013.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1014.         if(otg.req_length<(2*FS_CTRL_PKT_SIZE)) {
  1015.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+FS_CTRL_PKT_SIZE,
  1016.                         (otg.req_length-FS_CTRL_PKT_SIZE));
  1017.             otg.ep0_state = EP0_STATE_INIT;
  1018.         } else {
  1019.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+FS_CTRL_PKT_SIZE,
  1020.                         FS_CTRL_PKT_SIZE);
  1021.             otg.ep0_state = EP0_STATE_GD_DEV_2;
  1022.         }
  1023.         break;

  1025.     case EP0_STATE_GD_DEV_2:
  1026.         DBG_SETUP1("EP0_STATE_GD_DEV_2\n");
  1027.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1028.         if(otg.req_length<DEVICE_DESC_SIZE) {
  1029.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+(2*FS_CTRL_PKT_SIZE),
  1030.                         (otg.req_length-2*FS_CTRL_PKT_SIZE));
  1031.         } else {
  1032.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+(2*FS_CTRL_PKT_SIZE),
  1033.                         (DEVICE_DESC_SIZE-2*FS_CTRL_PKT_SIZE));
  1034.         }
  1035.         otg.ep0_state = EP0_STATE_INIT;
  1036.         break;

  1038.     /* GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 */
  1039.     case EP0_STATE_GD_CFG_0:
  1040.         DBG_SETUP1("EP0_STATE_GD_CFG_0 :");
  1041.         if (otg.speed == USB_HIGH)
  1042.         {
  1043.             DBG_SETUP1("High Speed\n");
  1044.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1045.             if(otg.req_length<CONFIG_DESC_TOTAL_SIZE)
  1046.             {
  1047.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1048.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1049.             }
  1050.             else
  1051.             {
  1052.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_TOTAL_SIZE);
  1053.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, CONFIG_DESC_TOTAL_SIZE);
  1054.             }
  1055.             otg.ep0_state = EP0_STATE_INIT;
  1056.         }
  1057.         else
  1058.         {
  1059.             DBG_SETUP1("Full Speed\n");
  1060.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1061.             if(otg.req_length<CONFIG_DESC_TOTAL_SIZE)
  1062.             {
  1063.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1064.             }
  1065.             else
  1066.             {
  1067.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_TOTAL_SIZE);
  1068.             }
  1069.             if(otg.req_length<FS_CTRL_PKT_SIZE)
  1070.             {
  1071.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1072.                 otg.ep0_state = EP0_STATE_INIT;
  1073.             }
  1074.             else
  1075.             {
  1076.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, FS_CTRL_PKT_SIZE);
  1077.                 otg.ep0_state = EP0_STATE_GD_CFG_1;
  1078.             }
  1079.         }
  1080.         break;

  1082.     case EP0_STATE_GD_CFG_1:
  1083.         DBG_SETUP1("EP0_STATE_GD_CFG_1\n");
  1084.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1085.         if(otg.req_length<(2*FS_CTRL_PKT_SIZE))
  1086.         {
  1087.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+FS_CTRL_PKT_SIZE,
  1088.                         (otg.req_length-FS_CTRL_PKT_SIZE));
  1089.             otg.ep0_state = EP0_STATE_INIT;
  1090.         }
  1091.         else
  1092.         {
  1093.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+FS_CTRL_PKT_SIZE,
  1094.                         FS_CTRL_PKT_SIZE);
  1095.             otg.ep0_state = EP0_STATE_GD_CFG_2;
  1096.         }
  1097.         break;

  1099.     case EP0_STATE_GD_CFG_2:
  1100.         DBG_SETUP1("EP0_STATE_GD_CFG_2\n");
  1101.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1102.         if(otg.req_length<(3*FS_CTRL_PKT_SIZE))
  1103.         {
  1104.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(2*FS_CTRL_PKT_SIZE),
  1105.                         (otg.req_length-2*FS_CTRL_PKT_SIZE));
  1106.             otg.ep0_state = EP0_STATE_INIT;
  1107.         }
  1108.         else
  1109.         {
  1110.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(2*FS_CTRL_PKT_SIZE),
  1111.                         FS_CTRL_PKT_SIZE);
  1112.             otg.ep0_state = EP0_STATE_GD_CFG_3;
  1113.         }
  1114.         break;

  1116.     case EP0_STATE_GD_CFG_3:
  1117.         DBG_SETUP1("EP0_STATE_GD_CFG_3\n");
  1118.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1119.         if(otg.req_length<(4*FS_CTRL_PKT_SIZE))
  1120.         {
  1121.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(3*FS_CTRL_PKT_SIZE),
  1122.                         (otg.req_length-3*FS_CTRL_PKT_SIZE));
  1123.             otg.ep0_state = EP0_STATE_INIT;
  1124.         }
  1125.         else
  1126.         {
  1127.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(3*FS_CTRL_PKT_SIZE),
  1128.                         FS_CTRL_PKT_SIZE);
  1129.             otg.ep0_state = EP0_STATE_GD_CFG_4;
  1130.         }
  1131.         break;

  1133.     case EP0_STATE_GD_CFG_4:
  1134.         DBG_SETUP1("EP0_STATE_GD_CFG_4\n");
  1135.         otg.ep0_state = EP0_STATE_INIT;
  1136.         break;

  1138.     case EP0_STATE_GD_DEV_QUALIFIER:    /*only supported in USB 2.0*/
  1139.         DBG_SETUP1("EP0_STATE_GD_DEV_QUALIFIER\n");
  1140.         writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1141.         if(otg.req_length<10)
  1142.         {
  1143.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1144.             s3c_usb_write_ep0_fifo((u8 *)qualifier_desc+0, otg.req_length);
  1145.         }
  1146.         else
  1147.         {
  1148.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 10);
  1149.             s3c_usb_write_ep0_fifo((u8 *)qualifier_desc+0, 10);
  1150.         }
  1151.         otg.ep0_state = EP0_STATE_INIT;
  1152.         break;

  1154.     case EP0_STATE_GD_OTHER_SPEED:
  1155.             DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED\n");
  1156.             s3c_usb_set_otherspeed_conf_desc(otg.req_length);
  1157.             break;

  1159.     case EP0_STATE_GD_OTHER_SPEED_HIGH_1:
  1160.         DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED_HIGH_1\n");
  1161.         if(otg.req_length==9)
  1162.         {
  1163.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1164.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1165.                 s3c_usb_write_ep0_fifo(((u8 *)&config_high)+8, 1);
  1166.                 otg.ep0_state = EP0_STATE_INIT;
  1167.         }
  1168.         else
  1169.         {
  1170.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  1171.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1172.                 s3c_usb_write_ep0_fifo(((u8 *)&config_high)+8, 8);
  1173.                 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_2;
  1174.         }
  1175.             break;

  1177.     case EP0_STATE_GD_OTHER_SPEED_HIGH_2:
  1178.         DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED_HIGH_2\n");
  1179.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  1180.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1181.             s3c_usb_write_ep0_fifo(((u8 *)&config_high)+16, 8);
  1182.             otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_3;
  1183.             break;

  1185.     case EP0_STATE_GD_OTHER_SPEED_HIGH_3:
  1186.         DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED_HIGH_3\n");
  1187.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  1188.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1189.             s3c_usb_write_ep0_fifo(((u8 *)&config_high)+24, 8);
  1190.             otg.ep0_state = EP0_STATE_INIT;
  1191.             break;

  1193.     /* GET_DESCRIPTOR:CONFIGURATION ONLY*/
  1194.     case EP0_STATE_GD_CFG_ONLY_0:
  1195.         DBG_SETUP1("EP0_STATE_GD_CFG_ONLY_0:");
  1196.         if (otg.speed == USB_HIGH)
  1197.         {
  1198.             DBG_SETUP1("High Speed\n");
  1199.             if(otg.req_length<CONFIG_DESC_SIZE)
  1200.             {
  1201.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1202.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1203.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1204.             }
  1205.             else
  1206.             {
  1207.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_SIZE);
  1208.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1209.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0,
  1210.                             CONFIG_DESC_SIZE);
  1211.             }
  1212.             otg.ep0_state = EP0_STATE_INIT;
  1213.         }
  1214.         else
  1215.         {
  1216.             DBG_SETUP1("Full Speed\n");
  1217.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1218.             if(otg.req_length<CONFIG_DESC_SIZE)
  1219.             {
  1220.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1221.             }
  1222.             else
  1223.             {
  1224.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_SIZE);
  1225.             }
  1226.             if(otg.req_length<FS_CTRL_PKT_SIZE)
  1227.             {
  1228.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1229.                 otg.ep0_state = EP0_STATE_INIT;
  1230.             }
  1231.             else
  1232.             {
  1233.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, FS_CTRL_PKT_SIZE);
  1234.                 otg.ep0_state = EP0_STATE_GD_CFG_ONLY_1;
  1235.             }
  1236.         }
  1237.         break;

  1239.     case EP0_STATE_GD_CFG_ONLY_1:
  1240.         DBG_SETUP1("EP0_STATE_GD_CFG_ONLY_1\n");
  1241.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1242.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+FS_CTRL_PKT_SIZE,
  1243.                     (CONFIG_DESC_SIZE-FS_CTRL_PKT_SIZE));
  1244.         otg.ep0_state = EP0_STATE_INIT;
  1245.         break;

  1247.     /* GET_DESCRIPTOR:INTERFACE ONLY */

  1249.     case EP0_STATE_GD_IF_ONLY_0:
  1250.         DBG_SETUP1("EP0_STATE_GD_IF_ONLY_0 :");
  1251.         if (otg.speed == USB_HIGH)
  1252.         {
  1253.             DBG_SETUP1("High Speed\n");
  1254.             if(otg.req_length<INTERFACE_DESC_SIZE)
  1255.             {
  1256.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1257.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1258.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, otg.req_length);
  1259.             }
  1260.             else
  1261.             {
  1262.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, INTERFACE_DESC_SIZE);
  1263.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1264.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, INTERFACE_DESC_SIZE);
  1265.             }
  1266.             otg.ep0_state = EP0_STATE_INIT;
  1267.         }
  1268.         else
  1269.         {
  1270.             DBG_SETUP1("Full Speed\n");
  1271.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1272.             if(otg.req_length<INTERFACE_DESC_SIZE)
  1273.             {
  1274.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1275.             }
  1276.             else
  1277.             {
  1278.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, INTERFACE_DESC_SIZE);
  1279.             }
  1280.             if(otg.req_length<FS_CTRL_PKT_SIZE)
  1281.             {
  1282.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, otg.req_length);
  1283.                 otg.ep0_state = EP0_STATE_INIT;
  1284.             }
  1285.             else
  1286.             {
  1287.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, FS_CTRL_PKT_SIZE);
  1288.                 otg.ep0_state = EP0_STATE_GD_IF_ONLY_1;
  1289.             }
  1290.         }
  1291.         break;

  1293.     case EP0_STATE_GD_IF_ONLY_1:
  1294.         DBG_SETUP1("EP0_STATE_GD_IF_ONLY_1\n");
  1295.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1296.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+FS_CTRL_PKT_SIZE,
  1297.                     (INTERFACE_DESC_SIZE-FS_CTRL_PKT_SIZE));
  1298.         otg.ep0_state = EP0_STATE_INIT;
  1299.         break;


  1302.     /* GET_DESCRIPTOR:ENDPOINT 1 ONLY */
  1303.     case EP0_STATE_GD_EP0_ONLY_0:
  1304.         DBG_SETUP1("EP0_STATE_GD_EP0_ONLY_0\n");
  1305.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1306.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
  1307.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.ep1))+0, ENDPOINT_DESC_SIZE);
  1308.         otg.ep0_state = EP0_STATE_INIT;
  1309.         break;

  1311.     /* GET_DESCRIPTOR:ENDPOINT 2 ONLY */
  1312.     case EP0_STATE_GD_EP1_ONLY_0:
  1313.         DBG_SETUP1("EP0_STATE_GD_EP1_ONLY_0\n");
  1314.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
  1315.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1316.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.ep2))+0, ENDPOINT_DESC_SIZE);
  1317.         otg.ep0_state = EP0_STATE_INIT;
  1318.         break;

  1320.     /* GET_DESCRIPTOR:STRING */
  1321.     case EP0_STATE_GD_STR_I0:
  1322.         DBG_SETUP1("EP0_STATE_GD_STR_I0\n");
  1323.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, STRING_DESC0_SIZE);
  1324.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1325.         s3c_usb_write_ep0_fifo((u8 *)string_desc0, STRING_DESC0_SIZE);
  1326.         otg.ep0_state = EP0_STATE_INIT;
  1327.         break;

  1329.     case EP0_STATE_GD_STR_I1:
  1330.         DBG_SETUP1("EP0_STATE_GD_STR_I1 %d\n", otg.ep0_substate);
  1331.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc1));
  1332.         if ((otg.ep0_substate*otg.ctrl_max_pktsize+otg.ctrl_max_pktsize)
  1333.             < sizeof(string_desc1)) {

  1335.             if (otg.speed == USB_HIGH)
  1336.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1337.             else
  1338.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1339.             s3c_usb_write_ep0_fifo((u8 *)string_desc1+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1340.                         otg.ctrl_max_pktsize);
  1341.             otg.ep0_state = EP0_STATE_GD_STR_I1;
  1342.             otg.ep0_substate++;
  1343.         } else {
  1344.             if (otg.speed == USB_HIGH)
  1345.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1346.             else
  1347.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1348.             s3c_usb_write_ep0_fifo((u8 *)string_desc1+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1349.                         sizeof(string_desc1)-(otg.ep0_substate*otg.ctrl_max_pktsize));
  1350.             otg.ep0_state = EP0_STATE_INIT;
  1351.             otg.ep0_substate = 0;
  1352.         }
  1353.         break;

  1355.     case EP0_STATE_GD_STR_I2:
  1356.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc2));
  1357.         if ((otg.ep0_substate*otg.ctrl_max_pktsize+otg.ctrl_max_pktsize)
  1358.             < sizeof(string_desc2)) {

  1360.             if (otg.speed == USB_HIGH)
  1361.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1362.             else
  1363.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1364.             s3c_usb_write_ep0_fifo((u8 *)string_desc2+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1365.                         otg.ctrl_max_pktsize);
  1366.             otg.ep0_state = EP0_STATE_GD_STR_I2;
  1367.             otg.ep0_substate++;
  1368.         } else {
  1369.             if (otg.speed == USB_HIGH)
  1370.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1371.             else
  1372.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1373.             s3c_usb_write_ep0_fifo((u8 *)string_desc2+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1374.                         sizeof(string_desc2)-(otg.ep0_substate*otg.ctrl_max_pktsize));
  1375.             otg.ep0_state = EP0_STATE_INIT;
  1376.             otg.ep0_substate = 0;
  1377.         }
  1378.         DBG_SETUP1("EP0_STATE_GD_STR_I2 %d", otg.ep0_substate);
  1379.         break;

  1381.     case EP0_STATE_INTERFACE_GET:
  1382.         DBG_SETUP1("EP0_STATE_INTERFACE_GET\n");
  1383.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1384.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1385.         s3c_usb_write_ep0_fifo((u8 *)&get_intf+0, 1);
  1386.         otg.ep0_state = EP0_STATE_INIT;
  1387.         break;


  1390.     case EP0_STATE_GET_STATUS0:
  1391.         DBG_SETUP1("EP0_STATE_GET_STATUS0\n");
  1392.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1393.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1394.         s3c_usb_write_ep0_fifo((u8 *)&get_status+0, 1);
  1395.         otg.ep0_state = EP0_STATE_INIT;
  1396.         break;

  1398.     case EP0_STATE_GET_STATUS1:
  1399.         DBG_SETUP1("EP0_STATE_GET_STATUS1\n");
  1400.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1401.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1402.         s3c_usb_write_ep0_fifo((u8 *)&get_status+1, 1);
  1403.         otg.ep0_state = EP0_STATE_INIT;
  1404.         break;

  1406.     case EP0_STATE_GET_STATUS2:
  1407.         DBG_SETUP1("EP0_STATE_GET_STATUS2\n");
  1408.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1409.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1410.         s3c_usb_write_ep0_fifo((u8 *)&get_status+2, 1);
  1411.         otg.ep0_state = EP0_STATE_INIT;
  1412.         break;

  1414.     case EP0_STATE_GET_STATUS3:
  1415.         DBG_SETUP1("EP0_STATE_GET_STATUS3\n");
  1416.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1417.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1418.         s3c_usb_write_ep0_fifo((u8 *)&get_status+3, 1);
  1419.         otg.ep0_state = EP0_STATE_INIT;
  1420.         break;

  1422.     case EP0_STATE_GET_STATUS4:
  1423.         DBG_SETUP1("EP0_STATE_GET_STATUS4\n");
  1424.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1425.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1426.         s3c_usb_write_ep0_fifo((u8 *)&get_status+4, 1);
  1427.         otg.ep0_state = EP0_STATE_INIT;
  1428.         break;

  1430.     default:
  1431.         break;
  1432.     }
  1433. }


  1436. void s3c_usb_int_bulkin(void)
  1437. {
  1438.     u8* bulkin_buf;
  1439.     u32 remain_cnt;

  1441.     DBG_BULK0("Bulk In Function\n");

  1443.     bulkin_buf = (u8*)otg.up_ptr;
  1444.     remain_cnt = otg.up_size- ((u32)otg.up_ptr - otg.up_addr);
  1445.     DBG_BULK1("bulkin_buf = 0x%x,remain_cnt = 0x%x \n", bulkin_buf, remain_cnt);

  1447.     if (remain_cnt > otg.bulkin_max_pktsize) {
  1448.         s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, otg.bulkin_max_pktsize);

  1450.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1451.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1452.             S5P_OTG_DIEPCTL_IN);

  1454.         s3c_usb_write_in_fifo(bulkin_buf, otg.bulkin_max_pktsize);

  1456.         otg.up_ptr += otg.bulkin_max_pktsize;

  1458.     } else if(remain_cnt > 0) {
  1459.         s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, remain_cnt);

  1461.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1462.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1463.             S5P_OTG_DIEPCTL_IN);

  1465.         s3c_usb_write_in_fifo(bulkin_buf, remain_cnt);

  1467.         otg.up_ptr += remain_cnt;

  1469.     } else { /*remain_cnt = 0*/
  1470.         writel((DEPCTL_SNAK|DEPCTL_BULK_TYPE), S5P_OTG_DIEPCTL_IN);
  1471.     }
  1472. }

  1474. void s3c_usb_upload_start(void)
  1475. {
  1476.     u8 tmp_buf[12];
  1477.     u32 check;

  1479.     s3c_usb_read_out_fifo((u8 *)tmp_buf, 10);
  1480.     check = *((u8 *)(tmp_buf+8)) + (*((u8 *)(tmp_buf+9))<<8);

  1482.     if (check==0x1) {
  1483.         otg.up_addr =
  1484.             *((u8 *)(tmp_buf+0))+
  1485.             (*((u8 *)(tmp_buf+1))<<8)+
  1486.             (*((u8 *)(tmp_buf+2))<<16)+
  1487.             (*((u8 *)(tmp_buf+3))<<24);

  1489.         otg.up_size =
  1490.             *((u8 *)(tmp_buf+4))+
  1491.             (*((u8 *)(tmp_buf+5))<<8)+
  1492.             (*((u8 *)(tmp_buf+6))<<16)+
  1493.             (*((u8 *)(tmp_buf+7))<<24);

  1495.         otg.up_ptr=(u8 *)otg.up_addr;
  1496.         DBG_BULK1("UploadAddress : 0x%x, UploadSize: %d\n",
  1497.             otg.up_addr, otg.up_size);

  1499.         if (otg.op_mode == USB_CPU) {
  1500.             if (otg.up_size > otg.bulkin_max_pktsize) {
  1501.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
  1502.                     otg.bulkin_max_pktsize);
  1503.             } else {
  1504.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
  1505.                     otg.up_size);
  1506.             }

  1508.             /*ep1 enable, clear nak, bulk, usb active, max pkt 64*/
  1509.             writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1510.                 S5P_OTG_DIEPCTL_IN);
  1511.         } else if ((otg.op_mode == USB_DMA) && (otg.up_size > 0)) {
  1512.             u32 pktcnt, remainder;

  1514.             DBG_BULK1("Dma Start for IN PKT \n");

  1516.             writel(MODE_DMA|BURST_INCR4|GBL_INT_UNMASK,
  1517.                 S5P_OTG_GAHBCFG);
  1518.             writel(INT_RESUME|INT_OUT_EP|INT_IN_EP| INT_ENUMDONE|
  1519.                 INT_RESET|INT_SUSPEND, S5P_OTG_GINTMSK);

  1521.             writel((u32)otg.up_ptr, S5P_OTG_DIEPDMA_IN);

  1523.             pktcnt = (u32)(otg.up_size/otg.bulkin_max_pktsize);
  1524.             remainder = (u32)(otg.up_size%otg.bulkin_max_pktsize);
  1525.             if(remainder != 0) {
  1526.                 pktcnt += 1;
  1527.             }

  1529.             if (pktcnt > 1023) {
  1530.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
  1531.                     (otg.bulkin_max_pktsize*1023));
  1532.             } else {
  1533.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
  1534.                     otg.up_size);
  1535.             }

  1537.             /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
  1538.             writel(1u<<31|1<<26|2<<18|1<<15|BULK_IN_EP<<11|
  1539.                 otg.bulkin_max_pktsize<<0,
  1540.                 S5P_OTG_DIEPCTL_IN);
  1541.         }
  1542.     }
  1543.     otg.dn_filesize=0;
  1544. }

  1546. void s3c_usb_download_start(u32 fifo_cnt_byte)
  1547. {
  1548.     u8 tmp_buf[8];

  1550.     s3c_usb_read_out_fifo((u8 *)tmp_buf, 8);
  1551.     DBG_BULK1("downloadFileSize==0, 1'st BYTE_READ_CNT_REG : %x\n",
  1552.         fifo_cnt_byte);

  1554.     otg.dn_addr=s3c_usbd_dn_addr;
  1555.     otg.dn_filesize=
  1556.         *((u8 *)(tmp_buf+4))+
  1557.         (*((u8 *)(tmp_buf+5))<<8)+
  1558.         (*((u8 *)(tmp_buf+6))<<16)+
  1559.         (*((u8 *)(tmp_buf+7))<<24);

  1561.     otg.dn_ptr=(u8 *)otg.dn_addr;
  1562.     DBG_BULK1("downloadAddress : 0x%x, downloadFileSize: %x\n",
  1563.         otg.dn_addr, otg.dn_filesize);

  1565.     /* The first 8-bytes are deleted.*/
  1566.     s3c_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte-8);
  1567.     otg.dn_ptr += fifo_cnt_byte-8;

  1569.     if (otg.op_mode == USB_CPU) {
  1570.         s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1,
  1571.             otg.bulkout_max_pktsize);

  1573.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1574.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1575.         S5P_OTG_DOEPCTL_OUT);
  1576.     } else if (otg.dn_filesize>otg.bulkout_max_pktsize) {
  1577.         u32 pkt_cnt, remain_cnt;

  1579.         DBG_BULK1("downloadFileSize!=0, Dma Start for 2nd OUT PKT \n");
  1580.         writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  1581.             INT_RESET|INT_SUSPEND, S5P_OTG_GINTMSK); /*gint unmask */
  1582.         writel(MODE_DMA|BURST_INCR4|GBL_INT_UNMASK,
  1583.             S5P_OTG_GAHBCFG);
  1584.         writel((u32)otg.dn_ptr, S5P_OTG_DOEPDMA_OUT);
  1585.         pkt_cnt = (u32)(otg.dn_filesize-otg.bulkout_max_pktsize)/otg.bulkout_max_pktsize;
  1586.         remain_cnt = (u32)((otg.dn_filesize-otg.bulkout_max_pktsize)%otg.bulkout_max_pktsize);
  1587.         if(remain_cnt != 0) {
  1588.             pkt_cnt += 1;
  1589.         }

  1591.         if (pkt_cnt > 1023) {
  1592.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
  1593.                 (otg.bulkout_max_pktsize*1023));
  1594.         } else {
  1595.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, pkt_cnt,
  1596.                 (otg.dn_filesize-otg.bulkout_max_pktsize));
  1597.         }

  1599.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1600.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1601.             S5P_OTG_DOEPCTL_OUT);
  1602.     }
  1603. }

  1605. void s3c_usb_download_continue(u32 fifo_cnt_byte)
  1606. {
  1607.     if (otg.op_mode == USB_CPU) {
  1608.         s3c_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte);
  1609.         otg.dn_ptr += fifo_cnt_byte;
  1610.         DBG_BULK1("downloadFileSize!=0, 2nd BYTE_READ_CNT_REG = 0x%x, m_pDownPt = 0x%x\n",
  1611.                 fifo_cnt_byte, otg.dn_ptr);

  1613.         s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);

  1615.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1616.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1617.             S5P_OTG_DOEPCTL_OUT);

  1619.         /* USB format : addr(4)+size(4)+data(n)+cs(2) */
  1620.         if (((u32)otg.dn_ptr - otg.dn_addr) >= (otg.dn_filesize - 8)) {
  1621.             printf("Download Done!! Download Address: 0x%x, Download Filesize:0x%x\n",
  1622.                 otg.dn_addr, (otg.dn_filesize-10));

  1624.             s3c_usbd_dn_cnt     = otg.dn_filesize-10;
  1625.             s3c_usbd_dn_addr    = otg.dn_addr;

  1627. #ifdef USB_CHECKSUM_EN
  1628.             s3c_usb_verify_checksum();
  1629. #endif
  1630.             s3c_receive_done = 1;
  1631.         }

  1633.     }\
  1634. }

  1636. void s3c_usb_int_bulkout(u32 fifo_cnt_byte)
  1637. {
  1638.     DBG_BULK0("Bulk Out Function : otg.dn_filesize=0x%x\n", otg.dn_filesize);
  1639.     if (otg.dn_filesize==0) {
  1640.         if (fifo_cnt_byte == 10) {
  1641.             s3c_usb_upload_start();
  1642.         } else {
  1643.             s3c_usb_download_start(fifo_cnt_byte);
  1644.         }
  1645.     } else {
  1646.         s3c_usb_download_continue(fifo_cnt_byte);
  1647.     }
  1648. }

  1650. void s3c_usb_dma_in_done(void)
  1651. {
  1652.     s32 remain_cnt;

  1654.     DBG_BULK0("DMA IN : Transfer Done\n");

  1656.     otg.up_ptr = (u8 *)readl(S5P_OTG_DIEPDMA_IN);
  1657.     remain_cnt = otg.up_size- ((u32)otg.up_ptr - otg.up_addr);

  1659.     if (remain_cnt>0) {
  1660.         u32 pktcnt, remainder;
  1661.         pktcnt = (u32)(remain_cnt/otg.bulkin_max_pktsize);
  1662.         remainder = (u32)(remain_cnt%otg.bulkin_max_pktsize);
  1663.         if(remainder != 0) {
  1664.             pktcnt += 1;
  1665.         }
  1666.         DBG_SETUP1("remain_cnt : %d \n", remain_cnt);
  1667.         if (pktcnt> 1023) {
  1668.             s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
  1669.                 (otg.bulkin_max_pktsize*1023));
  1670.         } else {
  1671.             s3c_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
  1672.                 remain_cnt);
  1673.         }

  1675.         /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
  1676.         writel(1u<<31|1<<26|2<<18|1<<15|BULK_IN_EP<<11|otg.bulkin_max_pktsize<<0,
  1677.             S5P_OTG_DIEPCTL_IN);
  1678.     } else
  1679.         DBG_SETUP1("DMA IN : Transfer Complete\n");
  1680. }

  1682. void s3c_usb_dma_out_done(void)
  1683. {
  1684.     s32 remain_cnt;

  1686.     DBG_BULK1("DMA OUT : Transfer Done\n");
  1687.     otg.dn_ptr = (u8 *)readl(S5P_OTG_DOEPDMA_OUT);

  1689.     remain_cnt = otg.dn_filesize - ((u32)otg.dn_ptr - otg.dn_addr + 8);

  1691.     if (remain_cnt>0) {
  1692.         u32 pktcnt, remainder;
  1693.         pktcnt = (u32)(remain_cnt/otg.bulkout_max_pktsize);
  1694.         remainder = (u32)(remain_cnt%otg.bulkout_max_pktsize);
  1695.         if(remainder != 0) {
  1696.             pktcnt += 1;
  1697.         }
  1698.         DBG_BULK1("remain_cnt : %d \n", remain_cnt);
  1699.         if (pktcnt> 1023) {
  1700.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
  1701.                 (otg.bulkout_max_pktsize*1023));
  1702.         } else {
  1703.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, pktcnt,
  1704.                 remain_cnt);
  1705.         }

  1707.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1708.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1709.             S5P_OTG_DOEPCTL_OUT);
  1710.     } else {
  1711.         DBG_BULK1("DMA OUT : Transfer Complete\n");
  1712.         udelay(500);        /*for FPGA ???*/
  1713.     }
  1714. }

  1716. void s3c_usb_set_all_outep_nak(void)
  1717. {
  1718.     u8 i;
  1719.     u32 tmp;

  1721.     for(i=0;i<16;i++)
  1722.     {
  1723.         tmp = readl(S5P_OTG_DOEPCTL0+0x20*i);
  1724.         tmp |= DEPCTL_SNAK;
  1725.         writel(tmp, S5P_OTG_DOEPCTL0+0x20*i);
  1726.     }
  1727. }

  1729. void s3c_usb_clear_all_outep_nak(void)
  1730. {
  1731.     u8 i;
  1732.     u32 tmp;

  1734.     for(i=0;i<16;i++)
  1735.     {
  1736.         tmp = readl(S5P_OTG_DOEPCTL0+0x20*i);
  1737.         tmp |= (DEPCTL_EPENA|DEPCTL_CNAK);
  1738.         writel(tmp, S5P_OTG_DOEPCTL0+0x20*i);
  1739.     }
  1740. }

  1742. void s3c_usb_set_max_pktsize(USB_SPEED speed)
  1743. {
  1744.     if (speed == USB_HIGH)
  1745.     {
  1746.         otg.speed = USB_HIGH;
  1747.         otg.ctrl_max_pktsize = HS_CTRL_PKT_SIZE;
  1748.         otg.bulkin_max_pktsize = HS_BULK_PKT_SIZE;
  1749.         otg.bulkout_max_pktsize = HS_BULK_PKT_SIZE;
  1750.     }
  1751.     else
  1752.     {
  1753.         otg.speed = USB_FULL;
  1754.         otg.ctrl_max_pktsize = FS_CTRL_PKT_SIZE;
  1755.         otg.bulkin_max_pktsize = FS_BULK_PKT_SIZE;
  1756.         otg.bulkout_max_pktsize = FS_BULK_PKT_SIZE;
  1757.     }
  1758. }

  1760. void s3c_usb_set_endpoint(void)
  1761. {
  1762.     /* Unmask S5P_OTG_DAINT source */
  1763.     writel(0xff, S5P_OTG_DIEPINT0);
  1764.     writel(0xff, S5P_OTG_DOEPINT0);
  1765.     writel(0xff, S5P_OTG_DIEPINT_IN);
  1766.     writel(0xff, S5P_OTG_DOEPINT_OUT);

  1768.     /* Init For Ep0*/
  1769.     if(otg.speed == USB_HIGH)
  1770.     {
  1771.         /*MPS:64bytes */
  1772.         writel(((1<<26)|(CONTROL_EP<<11)|(0<<0)), S5P_OTG_DIEPCTL0);
  1773.         /*ep0 enable, clear nak */
  1774.         writel((1u<<31)|(1<<26)|(0<<0), S5P_OTG_DOEPCTL0);
  1775.     }
  1776.     else
  1777.     {
  1778.         /*MPS:8bytes */
  1779.         writel(((1<<26)|(CONTROL_EP<<11)|(3<<0)), S5P_OTG_DIEPCTL0);
  1780.         /*ep0 enable, clear nak */
  1781.         writel((1u<<31)|(1<<26)|(3<<0), S5P_OTG_DOEPCTL0);
  1782.     }
  1783. }

  1785. void s3c_usb_set_descriptors(void)
  1786. {
  1787.     /* Standard device descriptor */
  1788.     otg.desc.dev.bLength=DEVICE_DESC_SIZE;    /*0x12*/
  1789.     otg.desc.dev.bDescriptorType=DEVICE_DESCRIPTOR;
  1790.     otg.desc.dev.bDeviceClass=0xFF; /* 0x0*/
  1791.     otg.desc.dev.bDeviceSubClass=0x0;
  1792.     otg.desc.dev.bDeviceProtocol=0x0;
  1793.     otg.desc.dev.bMaxPacketSize0=otg.ctrl_max_pktsize;
  1794.     otg.desc.dev.idVendorL=0xE8;    /*0x45;*/
  1795.     otg.desc.dev.idVendorH=0x04;    /*0x53;*/
  1796.     otg.desc.dev.idProductL=0x34; /*0x00*/
  1797.     otg.desc.dev.idProductH=0x12; /*0x64*/
  1798.     otg.desc.dev.bcdDeviceL=0x00;
  1799.     otg.desc.dev.bcdDeviceH=0x01;
  1800.     otg.desc.dev.iManufacturer=0x1; /* index of string descriptor */
  1801.     otg.desc.dev.iProduct=0x2;    /* index of string descriptor */
  1802.     otg.desc.dev.iSerialNumber=0x0;
  1803.     otg.desc.dev.bNumConfigurations=0x1;
  1804.     if (otg.speed == USB_FULL) {
  1805.         otg.desc.dev.bcdUSBL=0x10;
  1806.         otg.desc.dev.bcdUSBH=0x01;    /* Ver 1.10*/
  1807.     }
  1808.     else {
  1809.         otg.desc.dev.bcdUSBL=0x00;
  1810.         otg.desc.dev.bcdUSBH=0x02;    /* Ver 2.0*/
  1811.     }

  1813.     /* Standard configuration descriptor */
  1814.     otg.desc.config.bLength=CONFIG_DESC_SIZE; /* 0x9 bytes */
  1815.     otg.desc.config.bDescriptorType=CONFIGURATION_DESCRIPTOR;
  1816.     otg.desc.config.wTotalLengthL=CONFIG_DESC_TOTAL_SIZE;
  1817.     otg.desc.config.wTotalLengthH=0;
  1818.     otg.desc.config.bNumInterfaces=1;
  1819. /* dbg     descConf.bConfigurationValue=2; // why 2? There's no reason.*/
  1820.     otg.desc.config.bConfigurationValue=1;
  1821.     otg.desc.config.iConfiguration=0;
  1822.     otg.desc.config.bmAttributes=CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED; /* bus powered only.*/
  1823.     otg.desc.config.maxPower=25; /* draws 50mA current from the USB bus.*/

  1825.     /* Standard interface descriptor */
  1826.     otg.desc.intf.bLength=INTERFACE_DESC_SIZE; /* 9*/
  1827.     otg.desc.intf.bDescriptorType=INTERFACE_DESCRIPTOR;
  1828.     otg.desc.intf.bInterfaceNumber=0x0;
  1829.     otg.desc.intf.bAlternateSetting=0x0; /* ?*/
  1830.     otg.desc.intf.bNumEndpoints = 2;    /* # of endpoints except EP0*/
  1831.     otg.desc.intf.bInterfaceClass=0xff; /* 0x0 ?*/
  1832.     otg.desc.intf.bInterfaceSubClass=0x0;
  1833.     otg.desc.intf.bInterfaceProtocol=0x0;
  1834.     otg.desc.intf.iInterface=0x0;

  1836.     /* Standard endpoint0 descriptor */
  1837.     otg.desc.ep1.bLength=ENDPOINT_DESC_SIZE;
  1838.     otg.desc.ep1.bDescriptorType=ENDPOINT_DESCRIPTOR;
  1839.     otg.desc.ep1.bEndpointAddress=BULK_IN_EP|EP_ADDR_IN;
  1840.     otg.desc.ep1.bmAttributes=EP_ATTR_BULK;
  1841.     otg.desc.ep1.wMaxPacketSizeL=(u8)otg.bulkin_max_pktsize; /* 64*/
  1842.     otg.desc.ep1.wMaxPacketSizeH=(u8)(otg.bulkin_max_pktsize>>8);
  1843.     otg.desc.ep1.bInterval=0x0; /* not used */

  1845.     /* Standard endpoint1 descriptor */
  1846.     otg.desc.ep2.bLength=ENDPOINT_DESC_SIZE;
  1847.     otg.desc.ep2.bDescriptorType=ENDPOINT_DESCRIPTOR;
  1848.     otg.desc.ep2.bEndpointAddress=BULK_OUT_EP|EP_ADDR_OUT;
  1849.     otg.desc.ep2.bmAttributes=EP_ATTR_BULK;
  1850.     otg.desc.ep2.wMaxPacketSizeL=(u8)otg.bulkout_max_pktsize; /* 64*/
  1851.     otg.desc.ep2.wMaxPacketSizeH=(u8)(otg.bulkout_max_pktsize>>8);
  1852.     otg.desc.ep2.bInterval=0x0; /* not used */
  1853. }

  1855. void s3c_usb_check_speed(USB_SPEED *speed)
  1856. {
  1857.     u32 status;

  1859.     status = readl(S5P_OTG_DSTS); /* System status read */

  1861.     *speed = (USB_SPEED)((status&0x6) >>1);
  1862. }

  1864. void s3c_usb_clear_dnfile_info(void)
  1865. {
  1866.     otg.dn_addr = 0;
  1867.     otg.dn_filesize = 0;
  1868.     otg.dn_ptr = 0;
  1869. }

  1871. void s3c_usb_clear_upfile_info(void)
  1872. {
  1873.     otg.up_addr= 0;
  1874.     otg.up_size= 0;
  1875.     otg.up_ptr = 0;
  1876. }


  1879. int s3c_usb_check_setconf(void)
  1880. {
  1881.     if (otg.set_config == 0)
  1882.         return FALSE;
  1883.     else
  1884.         return TRUE;
  1885. }

  1887. void s3c_usb_set_opmode(USB_OPMODE mode)
  1888. {
  1889.     otg.op_mode = mode;

  1891.     writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  1892.         INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY,
  1893.         S5P_OTG_GINTMSK); /*gint unmask */

  1895.     writel(MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK, S5P_OTG_GAHBCFG);

  1897.     s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);
  1898.     s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, 0);

  1900.     /*bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt */
  1901.     writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1902.         S5P_OTG_DOEPCTL_OUT);

  1904.     /*bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt */
  1905.     writel(0u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1906.         S5P_OTG_DIEPCTL_IN);
  1907. }

  1909. void s3c_usb_reset(void)
  1910. {
  1911.     s3c_usb_set_all_outep_nak();

  1913.     otg.ep0_state = EP0_STATE_INIT;
  1914.     writel(((1<<BULK_OUT_EP)|(1<<CONTROL_EP))<<16|((1<<BULK_IN_EP)|(1<<CONTROL_EP)),
  1915.         S5P_OTG_DAINTMSK);
  1916.     writel(CTRL_OUT_EP_SETUP_PHASE_DONE|AHB_ERROR|TRANSFER_DONE,
  1917.         S5P_OTG_DOEPMSK);
  1918.     writel(INTKN_TXFEMP|NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE,
  1919.         S5P_OTG_DIEPMSK);

  1921.     /* Rx FIFO Size */
  1922.     writel(RX_FIFO_SIZE, S5P_OTG_GRXFSIZ);

  1924.     /* Non Periodic Tx FIFO Size */
  1925.     writel(NPTX_FIFO_SIZE<<16| NPTX_FIFO_START_ADDR<<0, S5P_OTG_GNPTXFSIZ);

  1927.     s3c_usb_clear_all_outep_nak();

  1929.     /*clear device address */
  1930.     writel(readl(S5P_OTG_DCFG)&~(0x7f<<4), S5P_OTG_DCFG);

  1932.     if(SUSPEND_RESUME_ON) {
  1933.         writel(readl(S5P_OTG_PCGCCTL)&~(1<<0), S5P_OTG_PCGCCTL);
  1934.     }
  1935. }
  1936. int s3c_usb_set_init(void)
  1937. {
  1938.     u32 status;

  1940.     status = readl(S5P_OTG_DSTS); /* System status read */

  1942.     /* Set if Device is High speed or Full speed */
  1943.     if (((status&0x6) >>1) == USB_HIGH) {
  1944.         DBG_SETUP1("High Speed Detection\n");
  1945.         s3c_usb_set_max_pktsize(USB_HIGH);
  1946.     }
  1947.     else if(((status&0x6) >>1) == USB_FULL) {
  1948.         DBG_SETUP1("Full Speed Detec tion\n");
  1949.         s3c_usb_set_max_pktsize(USB_FULL);
  1950.     }
  1951.     else {
  1952.         printf("**** Error:Neither High_Speed nor Full_Speed\n");
  1953.         return FALSE;
  1954.     }

  1956.     s3c_usb_set_endpoint();
  1957.     s3c_usb_set_descriptors();
  1958.     s3c_usb_clear_dnfile_info();
  1959.     s3c_usb_set_opmode(op_mode);

  1961.     return TRUE;
  1962. }

  1964. void s3c_usb_pkt_receive(void)
  1965. {
  1966.     u32 rx_status;
  1967.     u32 fifo_cnt_byte;

  1969.     rx_status = readl(S5P_OTG_GRXSTSP);
  1970.     DBG_SETUP0("S5P_OTG_GRXSTSP = 0x%x\n", rx_status);

  1972.     if ((rx_status & (0xf<<17)) == SETUP_PKT_RECEIVED) {
  1973.         DBG_SETUP1("SETUP_PKT_RECEIVED\n");
  1974.         s3c_usb_ep0_int_hndlr();

  1976.     } else if ((rx_status & (0xf<<17)) == OUT_PKT_RECEIVED) {
  1977.         fifo_cnt_byte = (rx_status & 0x7ff0)>>4;
  1978.         DBG_SETUP1("OUT_PKT_RECEIVED\n");

  1980.         if((rx_status & BULK_OUT_EP)&&(fifo_cnt_byte)) {
  1981.             s3c_usb_int_bulkout(fifo_cnt_byte);
  1982.             if( otg.op_mode == USB_CPU )
  1983.                 writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|
  1984.                     INT_ENUMDONE|INT_RESET|INT_SUSPEND|
  1985.                     INT_RX_FIFO_NOT_EMPTY,
  1986.                     S5P_OTG_GINTMSK);
  1987.             return;
  1988.         }

  1990.     } else if ((rx_status & (0xf<<17)) == GLOBAL_OUT_NAK) {
  1991.         DBG_SETUP1("GLOBAL_OUT_NAK\n");

  1993.     } else if ((rx_status & (0xf<<17)) == OUT_TRNASFER_COMPLETED) {
  1994.         DBG_SETUP1("OUT_TRNASFER_COMPLETED\n");

  1996.     } else if ((rx_status & (0xf<<17)) == SETUP_TRANSACTION_COMPLETED) {
  1997.         DBG_SETUP1("SETUP_TRANSACTION_COMPLETED\n");

  1999.     } else {
  2000.         DBG_SETUP1("Reserved\n");
  2001.     }
  2002. }

  2004. void s3c_usb_transfer(void)
  2005. {
  2006.     u32 ep_int;
  2007.     u32 check_dma;
  2008.     u32 ep_int_status;

  2010.     ep_int = readl(S5P_OTG_DAINT);
  2011.     DBG_SETUP0("S5P_OTG_DAINT = 0x%x", ep_int);

  2013.     if (ep_int & (1<<CONTROL_EP)) {
  2014.         ep_int_status = readl(S5P_OTG_DIEPINT0);
  2015.         DBG_SETUP1("S5P_OTG_DIEPINT0 : %x \n", ep_int_status);

  2017.         if (ep_int_status & INTKN_TXFEMP) {
  2018.             u32 uNTxFifoSpace;
  2019.             do {
  2020.                 uNTxFifoSpace=readl(S5P_OTG_GNPTXSTS)&0xffff;
  2021.             }while(uNTxFifoSpace<otg.ctrl_max_pktsize);

  2023.             s3c_usb_transfer_ep0();
  2024.         }

  2026.         writel(ep_int_status, S5P_OTG_DIEPINT0); /* Interrupt Clear */
  2027.     }

  2029.     if (ep_int & ((1<<CONTROL_EP)<<16)) {
  2030.         ep_int_status = readl(S5P_OTG_DOEPINT0);
  2031.         DBG_SETUP1("S5P_OTG_DOEPINT0 : %x \n", ep_int_status);

  2033.         s3c_usb_set_outep_xfersize(EP_TYPE_CONTROL, 1, 8);
  2034.         writel(1u<<31|1<<26, S5P_OTG_DOEPCTL0); /*ep0 enable, clear nak */

  2036.         writel(ep_int_status, S5P_OTG_DOEPINT0); /* Interrupt Clear */
  2037.     }

  2039.     if(ep_int & (1<<BULK_IN_EP)) {
  2040.         ep_int_status = readl(S5P_OTG_DIEPINT_IN);
  2041.         DBG_BULK1("S5P_OTG_DIEPINT_IN : %x \n", ep_int_status);
  2042.         writel(ep_int_status, S5P_OTG_DIEPINT_IN); /* Interrupt Clear */

  2044.         if ( (ep_int_status&INTKN_TXFEMP) && otg.op_mode == USB_CPU)
  2045.             s3c_usb_int_bulkin();

  2047.         check_dma = readl(S5P_OTG_GAHBCFG);
  2048.         if ((check_dma&MODE_DMA)&&(ep_int_status&TRANSFER_DONE))
  2049.             s3c_usb_dma_in_done();
  2050.     }

  2052.     if (ep_int & ((1<<BULK_OUT_EP)<<16)) {
  2053.         ep_int_status = readl(S5P_OTG_DOEPINT_OUT);
  2054.         DBG_BULK1("S5P_OTG_DOEPINT_OUT : 0x%x\n", ep_int_status);
  2055.         writel(ep_int_status, S5P_OTG_DOEPINT_OUT); /* Interrupt Clear */

  2057.         check_dma = readl(S5P_OTG_GAHBCFG);
  2058.         if ((check_dma&MODE_DMA)&&(ep_int_status&TRANSFER_DONE)) {
  2059.             s3c_usb_dma_out_done();
  2060.         }
  2061.     }
  2062. }

  2064. void s3c_udc_int_hndlr(void)
  2065. {
  2066.     u32 int_status;
  2067.     int tmp;

  2069.     int_status = readl(S5P_OTG_GINTSTS); /* Core Interrupt Register */
  2070.     writel(int_status, S5P_OTG_GINTSTS); /* Interrupt Clear */
  2071.     DBG_SETUP0("*** USB OTG Interrupt(S5P_OTG_GINTSTS: 0x%08x) ****\n",
  2072.         int_status);

  2074.     if (int_status & INT_RESET) {
  2075.         DBG_SETUP1("INT_RESET\n");
  2076.         writel(INT_RESET, S5P_OTG_GINTSTS); /* Interrupt Clear */

  2078.         s3c_usb_reset();
  2079.     }

  2081.     if (int_status & INT_ENUMDONE) {
  2082.         DBG_SETUP1("INT_ENUMDONE :");
  2083.         writel(INT_ENUMDONE, S5P_OTG_GINTSTS); /* Interrupt Clear */
  2084.         s3c_usb_connected_status=3;
  2085.         tmp = s3c_usb_set_init();
  2086.         if (tmp == FALSE)
  2087.             return;

  2089.     }

  2091.     if (int_status & INT_RESUME) {
  2092.         DBG_SETUP1("INT_RESUME\n");
  2093.         writel(INT_RESUME, S5P_OTG_GINTSTS); /* Interrupt Clear */

  2095.         if(SUSPEND_RESUME_ON) {
  2096.             writel(readl(S5P_OTG_PCGCCTL)&~(1<<0), S5P_OTG_PCGCCTL);
  2097.             DBG_SETUP1("INT_RESUME\n");
  2098.         }
  2099.     }

  2101.     if (int_status & INT_SUSPEND) {
  2102.         DBG_SETUP1("INT_SUSPEND\n");
  2103.         writel(INT_SUSPEND, S5P_OTG_GINTSTS); /* Interrupt Clear */

  2105.         if(SUSPEND_RESUME_ON) {
  2106.             writel(readl(S5P_OTG_PCGCCTL)|(1<<0), S5P_OTG_PCGCCTL);
  2107.         }
  2108.     }

  2110.     if(int_status & INT_RX_FIFO_NOT_EMPTY) {
  2111.         DBG_SETUP1("INT_RX_FIFO_NOT_EMPTY\n");
  2112.         /* Read only register field */

  2114.         writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|
  2115.             INT_ENUMDONE|INT_RESET|INT_SUSPEND,
  2116.             S5P_OTG_GINTMSK);
  2117.         s3c_usb_pkt_receive();
  2118.         writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  2119.             INT_RESET |INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY,
  2120.             S5P_OTG_GINTMSK); /*gint unmask */
  2121.         s3c_usb_connected_status=1;
  2122.     }

  2124.     if ((int_status & INT_IN_EP) || (int_status & INT_OUT_EP)) {
  2125.         DBG_SETUP1("INT_IN or OUT_EP\n");
  2126.         /* Read only register field */

  2128.         s3c_usb_transfer();
  2129.     }
  2130. }

  2132. int s3c_udc_is_adc_cable()
  2133. {
  2134.     int count = 0;
  2135.     while(count<10)
  2136.         {
  2137.     if((readl(S5P_OTG_HPRT)&0xc00)==0xc00)
  2138.         count ++;
  2139.     else
  2140.         {
  2141.             count =0;
  2142.             return 0;
  2143.         }
  2144.     }
  2145.     return 1;
  2146. }
  2147. /*the following is for u-boot battery charge*/
  2148. int s3c_check_usb_connect_status()
  2149. {
  2150.     if(!s3c_usb_phy_inited)/*initalized at first*/
  2151.     {    
  2152.         s3c_usbctl_init(1);
  2153.     }
  2154.     /*then check current usb status*/
  2155.     unsigned long usec = (1000*1000*10);
  2156.     ulong tmo, tmp;

  2158.     if (usec >= 1000) {        /* if "big" number, spread normalization to seconds */
  2159.         tmo = usec / 1000;    /* start to normalize for usec to ticks per sec */
  2160.         tmo *= CFG_HZ;        /* find number of "ticks" to wait to achieve target */
  2161.         tmo /= 1000;        /* finish normalize. */
  2162.     }
  2163.     else {                /* else small number, don't kill it prior to HZ multiply */
  2164.         tmo = usec * CFG_HZ;
  2165.         tmo /= (1000 * 1000);
  2166.     }
  2167.     tmp = get_timer(0);        /* get current timestamp */
  2168.     if ((tmo + tmp + 1) < tmp)    /* if setting this fordward will roll time stamp */
  2169.     {        
  2170.         reset_timer_masked();    /* reset "advancing" timestamp to 0, set lastdec value */
  2171.     }
  2172.     else
  2173.         tmo += tmp;        /* else, set advancing stamp wake up time */

  2175.     while (get_timer_masked()<tmo)    
  2176.     {
  2177.         if (S3C_USBD_DETECT_IRQ()) {
  2178.             s3c_udc_int_hndlr();
  2179.             S3C_USBD_CLEAR_IRQ();
  2180.         }
  2181.         if(s3c_udc_is_adc_cable())
  2182.             s3c_usb_connected_status=2;
  2183.         if(s3c_usb_connected_status==2||s3c_usb_connected_status==1)
  2184.             break;
  2185.     }
  2186.     
  2187.     if(s3c_usb_phy_inited)
  2188.     {        
  2189.         s3c_usb_stop();
  2190.     }
  2191.     return s3c_usb_connected_status;
  2192.     
  2193. }
  2194. #endif


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  1. /*
  2.  * cpu/s5pc1xx/usbd-otg-hs.c
  3.  *
  4.  * (C) Copyright 2007
  5.  * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
  6.  *    - only support for S5PC100
  7.  *
  8.  * This program is free software; you can redistribute it and/or
  9.  * modify it under the terms of the GNU General Public License as
  10.  * published by the Free Software Foundation; either version 2 of
  11.  * the License, or (at your option) any later version.
  12.  *
  13.  * This program is distributed in the hope that it will be useful,
  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16.  * GNU General Public License for more details.
  17.  *
  18.  * You should have received a copy of the GNU General Public License
  19.  * along with this program; if not, write to the Free Software
  20.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21.  * MA 02111-1307 USA
  22.  */

  24. #include <common.h>

  26. #if defined(CONFIG_S5PC110)
  27. #include <command.h>
  28. #include <asm/errno.h>
  29. #include <asm/io.h>
  30. #include <regs.h>
  31. #include "usbd-otg-hs.h"

  33. #undef USB_OTG_DEBUG_SETUP
  34. #ifdef USB_OTG_DEBUG_SETUP
  35. #define DBG_SETUP0(fmt, args...) printf("[%s:%d] " fmt, __FUNCTION__, __LINE__, ##args)
  36. #define DBG_SETUP1(fmt, args...) printf("\t" fmt, ##args)
  37. #define DBG_SETUP2(fmt, args...) printf(fmt, ##args)
  38. #else
  39. #define DBG_SETUP0(fmt, args...) do { } while (0)
  40. #define DBG_SETUP1(fmt, args...) do { } while (0)
  41. #define DBG_SETUP2(fmt, args...) do { } while (0)
  42. #endif

  44. #undef USB_OTG_DEBUG_BULK
  45. #ifdef USB_OTG_DEBUG_BULK
  46. #define DBG_BULK0(fmt, args...) printf("[%s:%d] " fmt, __FUNCTION__, __LINE__, ##args)
  47. #define DBG_BULK1(fmt, args...)    printf("\t" fmt, ##args)
  48. #else
  49. #define DBG_BULK0(fmt, args...) do { } while (0)
  50. #define DBG_BULK1(fmt, args...) do { } while (0)
  51. #endif

  53. #define USB_CHECKSUM_EN

  55. #define TRUE    1
  56. #define FALSE    0
  57. #define SUSPEND_RESUME_ON FALSE

  59. u32 s3c_usbd_dn_addr = 0;
  60. u32 s3c_usbd_dn_cnt = 0;
  61. u32 remode_wakeup;
  62. u16 config_value;

  64. int DNW;
  65. int s3c_receive_done = 0;
  66. int s3c_got_header = 0;
  67. int s3c_usb_phy_inited=0;
  68. int s3c_usb_connected_status= 0;/*0,none,1,usb connected,2,power connected,3,bad usb connected*/
  69. USB_OPMODE    op_mode = USB_CPU;
  70. USB_SPEED    speed = USB_HIGH;

  72. otg_dev_t    otg;
  73. get_status_t    get_status;
  74. get_intf_t    get_intf;

  76. enum EP_INDEX
  77. {
  78.     EP0, EP1, EP2, EP3, EP4
  79. };

  81. /*------------------------------------------------*/
  82. /* EP0 state */
  83. enum EP0_STATE
  84. {
  85.     EP0_STATE_INIT            = 0,
  86.     EP0_STATE_GD_DEV_0        = 11,
  87.     EP0_STATE_GD_DEV_1        = 12,
  88.     EP0_STATE_GD_DEV_2        = 13,
  89.     EP0_STATE_GD_CFG_0        = 21,
  90.     EP0_STATE_GD_CFG_1        = 22,
  91.     EP0_STATE_GD_CFG_2        = 23,
  92.     EP0_STATE_GD_CFG_3        = 24,
  93.     EP0_STATE_GD_CFG_4        = 25,
  94.     EP0_STATE_GD_STR_I0        = 30,
  95.     EP0_STATE_GD_STR_I1        = 31,
  96.     EP0_STATE_GD_STR_I2        = 32,
  97.     EP0_STATE_GD_DEV_QUALIFIER    = 33,
  98.     EP0_STATE_INTERFACE_GET        = 34,
  99.     EP0_STATE_GET_STATUS0        = 35,
  100.     EP0_STATE_GET_STATUS1        = 36,
  101.     EP0_STATE_GET_STATUS2        = 37,
  102.     EP0_STATE_GET_STATUS3        = 38,
  103.     EP0_STATE_GET_STATUS4        = 39,
  104.     EP0_STATE_GD_OTHER_SPEED    = 40,
  105.     EP0_STATE_GD_CFG_ONLY_0     = 41,
  106.     EP0_STATE_GD_CFG_ONLY_1     = 42,
  107.     EP0_STATE_GD_IF_ONLY_0        = 44,
  108.     EP0_STATE_GD_IF_ONLY_1        = 45,
  109.     EP0_STATE_GD_EP0_ONLY_0     = 46,
  110.     EP0_STATE_GD_EP1_ONLY_0     = 47,
  111.     EP0_STATE_GD_EP2_ONLY_0     = 48,
  112.     EP0_STATE_GD_EP3_ONLY_0     = 49,
  113.     EP0_STATE_GD_OTHER_SPEED_HIGH_1    = 51,
  114.     EP0_STATE_GD_OTHER_SPEED_HIGH_2    = 52,
  115.     EP0_STATE_GD_OTHER_SPEED_HIGH_3    = 53
  116. };

  118. /*definitions related to CSR setting */

  120. /* S5P_OTG_GOTGCTL*/
  121. #define B_SESSION_VALID        (0x1<<19)
  122. #define A_SESSION_VALID        (0x1<<18)

  124. /* S5P_OTG_GAHBCFG*/
  125. #define PTXFE_HALF        (0<<8)
  126. #define PTXFE_ZERO        (1<<8)
  127. #define NPTXFE_HALF        (0<<7)
  128. #define NPTXFE_ZERO        (1<<7)
  129. #define MODE_SLAVE        (0<<5)
  130. #define MODE_DMA        (1<<5)
  131. #define BURST_SINGLE        (0<<1)
  132. #define BURST_INCR        (1<<1)
  133. #define BURST_INCR4        (3<<1)
  134. #define BURST_INCR8        (5<<1)
  135. #define BURST_INCR16        (7<<1)
  136. #define GBL_INT_UNMASK        (1<<0)
  137. #define GBL_INT_MASK        (0<<0)

  139. /* S5P_OTG_GRSTCTL*/
  140. #define AHB_MASTER_IDLE        (1u<<31)
  141. #define CORE_SOFT_RESET        (0x1<<0)

  143. /* S5P_OTG_GINTSTS/S5P_OTG_GINTMSK core interrupt register */
  144. #define INT_RESUME        (1u<<31)
  145. #define INT_DISCONN        (0x1<<29)
  146. #define INT_CONN_ID_STS_CNG    (0x1<<28)
  147. #define INT_OUT_EP        (0x1<<19)
  148. #define INT_IN_EP        (0x1<<18)
  149. #define INT_ENUMDONE        (0x1<<13)
  150. #define INT_RESET        (0x1<<12)
  151. #define INT_SUSPEND        (0x1<<11)
  152. #define INT_TX_FIFO_EMPTY    (0x1<<5)
  153. #define INT_RX_FIFO_NOT_EMPTY    (0x1<<4)
  154. #define INT_SOF            (0x1<<3)
  155. #define INT_DEV_MODE        (0x0<<0)
  156. #define INT_HOST_MODE        (0x1<<1)

  158. /* S5P_OTG_GRXSTSP STATUS*/
  159. #define GLOBAL_OUT_NAK            (0x1<<17)
  160. #define OUT_PKT_RECEIVED        (0x2<<17)
  161. #define OUT_TRNASFER_COMPLETED        (0x3<<17)
  162. #define SETUP_TRANSACTION_COMPLETED    (0x4<<17)
  163. #define SETUP_PKT_RECEIVED        (0x6<<17)

  165. /* S5P_OTG_DCTL device control register */
  166. #define NORMAL_OPERATION        (0x1<<0)
  167. #define SOFT_DISCONNECT            (0x1<<1)
  168. #define    TEST_J_MODE            (TEST_J<<4)
  169. #define    TEST_K_MODE            (TEST_K<<4)
  170. #define    TEST_SE0_NAK_MODE        (TEST_SE0_NAK<<4)
  171. #define    TEST_PACKET_MODE        (TEST_PACKET<<4)
  172. #define    TEST_FORCE_ENABLE_MODE        (TEST_FORCE_ENABLE<<4)
  173. #define TEST_CONTROL_FIELD        (0x7<<4)

  175. /* S5P_OTG_DAINT device all endpoint interrupt register */
  176. #define INT_IN_EP0            (0x1<<0)
  177. #define INT_IN_EP1            (0x1<<1)
  178. #define INT_IN_EP3            (0x1<<3)
  179. #define INT_OUT_EP0            (0x1<<16)
  180. #define INT_OUT_EP2            (0x1<<18)
  181. #define INT_OUT_EP4            (0x1<<20)

  183. /* S5P_OTG_DIEPCTL0/S5P_OTG_DOEPCTL0 */
  184. #define DEPCTL_EPENA            (0x1<<31)
  185. #define DEPCTL_EPDIS            (0x1<<30)
  186. #define DEPCTL_SNAK            (0x1<<27)
  187. #define DEPCTL_CNAK            (0x1<<26)
  188. #define DEPCTL_CTRL_TYPE        (EP_TYPE_CONTROL<<18)
  189. #define DEPCTL_ISO_TYPE            (EP_TYPE_ISOCHRONOUS<<18)
  190. #define DEPCTL_BULK_TYPE        (EP_TYPE_BULK<<18)
  191. #define DEPCTL_INTR_TYPE        (EP_TYPE_INTERRUPT<<18)
  192. #define DEPCTL_USBACTEP            (0x1<<15)

  194. /*ep0 enable, clear nak, next ep0, max 64byte */
  195. #define EPEN_CNAK_EP0_64 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(0<<0))

  197. /*ep0 enable, clear nak, next ep0, 8byte */
  198. #define EPEN_CNAK_EP0_8 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(3<<0))

  200. /* DIEPCTLn/DOEPCTLn */
  201. #define BACK2BACK_SETUP_RECEIVED    (0x1<<6)
  202. #define INTKN_TXFEMP            (0x1<<4)
  203. #define NON_ISO_IN_EP_TIMEOUT        (0x1<<3)
  204. #define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
  205. #define AHB_ERROR            (0x1<<2)
  206. #define TRANSFER_DONE            (0x1<<0)


  209. /* codes representing languages */
  210. const u8 string_desc0[] =
  211. {
  212.     4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H,
  213. };

  215. const u8 string_desc1[] = /* Manufacturer */
  216. {
  217.     (0x14+2), STRING_DESCRIPTOR,
  218.     'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0,
  219.     'm', 0x0, ' ', 0x0, 'M', 0x0, 'C', 0x0, 'U', 0x0,
  220. };

  222. const u8 string_desc2[] = /* Product */
  223. {
  224.     (0x2a+2), STRING_DESCRIPTOR,
  225.     'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0,
  226.     '3', 0x0, 'C', 0x0, '6', 0x0, '4', 0x0, '0', 0x0,
  227.     '0', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0,
  228.     's', 0x0, 't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0,
  229.     'D', 0x0
  230. };

  232. /* setting the device qualifier descriptor and a string descriptor */
  233. const u8 qualifier_desc[] =
  234. {
  235.     0x0a,    /* 0 desc size */
  236.     0x06,    /* 1 desc type (DEVICE_QUALIFIER)*/
  237.     0x00,    /* 2 USB release */
  238.     0x02,    /* 3 => 2.00*/
  239.     0xFF,    /* 4 class */
  240.     0x00,    /* 5 subclass */
  241.     0x00,    /* 6 protocol */
  242.     64,    /* 7 max pack size */
  243.     0x01,    /* 8 number of other-speed configuration */
  244.     0x00,    /* 9 reserved */
  245. };

  247. const u8 config_full[] =
  248. {
  249.     0x09,    /* 0 desc size */
  250.     0x07,    /* 1 desc type (other speed)*/
  251.     0x20,    /* 2 Total length of data returned */
  252.     0x00,    /* 3 */
  253.     0x01,    /* 4 Number of interfaces supported by this speed configuration */
  254.     0x01,    /* 5 value to use to select configuration */
  255.     0x00,    /* 6 index of string desc */
  256.         /* 7 same as configuration desc */
  257.     CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED,
  258.     0x19,    /* 8 same as configuration desc */

  260. };

  262. const u8 config_full_total[] =
  263. {
  264.   0x09, 0x07 ,0x20 ,0x00 ,0x01 ,0x01 ,0x00 ,0xC0 ,0x19,
  265.   0x09 ,0x04 ,0x00 ,0x00 ,0x02 ,0xff ,0x00 ,0x00 ,0x00,
  266.   0x07 ,0x05 ,0x83 ,0x02 ,0x40 ,0x00 ,0x00,
  267.   0x07 ,0x05 ,0x04 ,0x02 ,0x40 ,0x00 ,0x00
  268. };

  270. const u8 config_high[] =
  271. {
  272.     0x09,    /* 0 desc size */
  273.     0x07,    /* 1 desc type (other speed)*/
  274.     0x20,    /* 2 Total length of data returned */
  275.     0x00,    /* 3 */
  276.     0x01,    /* 4 Number of interfaces supported by this speed configuration */
  277.     0x01,    /* 5 value to use to select configuration */
  278.     0x00,    /* 6 index of string desc */
  279.         /* 7 same as configuration desc */
  280.     CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED,
  281.     0x19,    /* 8 same as configuration desc */

  283. };

  285. const u8 config_high_total[] =
  286. {
  287.   0x09, 0x07 ,0x20 ,0x00 ,0x01 ,0x01 ,0x00 ,0xC0 ,0x19,
  288.   0x09 ,0x04 ,0x00 ,0x00 ,0x02 ,0xff ,0x00 ,0x00 ,0x00,
  289.   0x07 ,0x05 ,0x81 ,0x02 ,0x00 ,0x02 ,0x00,
  290.   0x07 ,0x05 ,0x02 ,0x02 ,0x00 ,0x02 ,0x00
  291. };

  293. /* Descriptor size */
  294. enum DESCRIPTOR_SIZE
  295. {
  296.     DEVICE_DESC_SIZE    = sizeof(device_desc_t),
  297.     STRING_DESC0_SIZE    = sizeof(string_desc0),
  298.     STRING_DESC1_SIZE    = sizeof(string_desc1),
  299.     STRING_DESC2_SIZE    = sizeof(string_desc2),
  300.     CONFIG_DESC_SIZE    = sizeof(config_desc_t),
  301.     INTERFACE_DESC_SIZE    = sizeof(intf_desc_t),
  302.     ENDPOINT_DESC_SIZE    = sizeof(ep_desc_t),
  303.     DEVICE_QUALIFIER_SIZE    = sizeof(qualifier_desc),
  304.     OTHER_SPEED_CFG_SIZE    = 9

  306. };

  308. /*32 <cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>*/
  309. #define CONFIG_DESC_TOTAL_SIZE    \
  310.     (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2)
  311. #define TEST_PKT_SIZE 53

  313. u8 test_pkt [TEST_PKT_SIZE] = {
  314.     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,    /*JKJKJKJK x 9*/
  315.     0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,    /*JJKKJJKK x 8*/
  316.     0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,    /*JJJJKKKK x 8*/
  317.     0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,    /*JJJJJJJKKKKKKK x8 - '1'*/
  318.     0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,        /*'1' + JJJJJJJK x 8*/
  319.     0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E    /*{JKKKKKKK x 10},JK*/
  320. };

  322. void s3c_usb_init_phy(void)
  323. {
  324.     writel(readl(USB_PHY_CONTROL)|(1<<0), USB_PHY_CONTROL);    /*USB PHY0 Enable */
  325.     
  326.     writel(0xa0, S5P_OTG_PHYPWR);
  327.     writel(0x3, S5P_OTG_PHYCLK);
  328.     writel(0x1, S5P_OTG_RSTCON);
  329.     udelay(10);
  330.     writel(0x0, S5P_OTG_RSTCON);
  331.     udelay(10);

  333. }

  335. /* OTG PHY Power Off */
  336. void s3c_usb_phy_off(void) {
  337.     writel(readl(S5P_OTG_PHYPWR)|(0x18), S5P_OTG_PHYPWR);
  338.     writel(readl(USB_PHY_CONTROL)&~(1<<0), USB_PHY_CONTROL);
  339.     s3c_usb_phy_inited=0;
  340. }

  342. void s3c_usb_core_soft_reset(void)
  343. {
  344.     u32 tmp;

  346.     writel(CORE_SOFT_RESET, S5P_OTG_GRSTCTL);

  348.     do
  349.     {
  350.         tmp = readl(S5P_OTG_GRSTCTL);
  351.     }while(!(tmp & AHB_MASTER_IDLE));

  353. }

  355. void s3c_usb_wait_cable_insert(void)
  356. {
  357.     u32 tmp;
  358.     int ucFirst=1;

  360.     do {
  361.         udelay(50);

  363.         tmp = readl(S5P_OTG_GOTGCTL);

  365.         if (tmp & (B_SESSION_VALID|A_SESSION_VALID)) {
  366.             printf("OTG cable Connected!\n");
  367.             break;
  368.         } else if(ucFirst == 1) {
  369.             printf("Insert a OTG cable into the connector!\n");
  370.             ucFirst = 0;
  371.         }
  372.     } while(1);
  373. }

  375. void s3c_usb_init_core(void)
  376. {
  377.     writel(PTXFE_HALF|NPTXFE_HALF|MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK,
  378.         S5P_OTG_GAHBCFG);

  380.     writel( 0<<15        /* PHY Low Power Clock sel */
  381.         |1<<14        /* Non-Periodic TxFIFO Rewind Enable */
  382.         |0x5<<10    /* Turnaround time */
  383.         |0<<9        /* 0:HNP disable, 1:HNP enable */
  384.         |0<<8        /* 0:SRP disable, 1:SRP enable */
  385.         |0<<7        /* ULPI DDR sel */
  386.         |0<<6        /* 0: high speed utmi+, 1: full speed serial */
  387.         |0<<4        /* 0: utmi+, 1:ulpi */
  388.         |1<<3        /* phy i/f 0:8bit, 1:16bit */
  389.         |0x7<<0,    /* HS/FS Timeout**/
  390.         S5P_OTG_GUSBCFG );
  391. }

  393. void s3c_usb_check_current_mode(u8 *pucMode)
  394. {
  395.     u32 tmp;

  397.     tmp = readl(S5P_OTG_GINTSTS);
  398.     *pucMode = tmp & 0x1;
  399. }

  401. void s3c_usb_set_soft_disconnect(void)
  402. {
  403.     u32 tmp;

  405.     tmp = readl(S5P_OTG_DCTL);
  406.     tmp |= SOFT_DISCONNECT;
  407.     writel(tmp, S5P_OTG_DCTL);
  408. }

  410. void s3c_usb_clear_soft_disconnect(void)
  411. {
  412.     u32 tmp;

  414.     tmp = readl(S5P_OTG_DCTL);
  415.     tmp &= ~SOFT_DISCONNECT;
  416.     writel(tmp, S5P_OTG_DCTL);
  417. }

  419. void s3c_usb_init_device(void)
  420. {
  421.     writel(1<<18|otg.speed<<0, S5P_OTG_DCFG); /* [][1: full speed(30Mhz) 0:high speed]*/

  423.     writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  424.         INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY,
  425.         S5P_OTG_GINTMSK);    /*gint unmask */
  426.     s3c_usb_phy_inited=1;
  427. }

  429. int s3c_usbctl_init(int ischeckstatus)/*diog, if not for check status, donot need wait cable insert*/
  430. {
  431.     u8 ucMode;

  433.     DBG_SETUP0("USB Control Init\n");
  434.     
  435.     otg.speed = speed;
  436.     otg.set_config = 0;
  437.     otg.ep0_state = EP0_STATE_INIT;
  438.     otg.ep0_substate = 0;
  439.     s3c_usb_init_phy();
  440.     s3c_usb_core_soft_reset();
  441.     if(!ischeckstatus)
  442.     s3c_usb_wait_cable_insert();
  443.     s3c_usb_init_core();
  444.     s3c_usb_check_current_mode(&ucMode);

  446.     if (ucMode == INT_DEV_MODE) {
  447.         s3c_usb_set_soft_disconnect();
  448.         udelay(10);
  449.         s3c_usb_clear_soft_disconnect();
  450.         s3c_usb_init_device();
  451.         return 0;
  452.     } else {
  453.         printf("Error : Current Mode is Host\n");
  454.         return 0;
  455.     }
  456. }

  458. int s3c_usbc_activate (void)
  459. {
  460.     /* dont used in usb high speed, but used in common file cmd_usbd.c */
  461.     return 0;
  462. }

  464. int s3c_usb_stop (void)
  465. {
  466.     /* dont used in usb high speed, but used in common file cmd_usbd.c */
  467.     s3c_usb_core_soft_reset();
  468.     s3c_usb_phy_off();
  469.     return 0;
  470. }

  472. void s3c_usb_print_pkt(u8 *pt, u8 count)
  473. {
  474.     int i;
  475.     printf("[s3c_usb_print_pkt:");

  477.     for(i=0;i<count;i++)
  478.         printf("%x,", pt[i]);

  480.     printf("]\n");
  481. }

  483. void s3c_usb_verify_checksum(void)
  484. {
  485.     u8 *cs_start, *cs_end;
  486.     u16 dnCS;
  487.     u16 checkSum;

  489.     printf("Checksum is being calculated.");

  491.     /* checksum calculation */
  492.     cs_start = (u8*)otg.dn_addr;
  493.     cs_end = (u8*)(otg.dn_addr+otg.dn_filesize-10);
  494.     checkSum = 0;
  495.     while(cs_start < cs_end) {
  496.         checkSum += *cs_start++;
  497.         if(((u32)cs_start&0xfffff)==0) printf(".");
  498.     }

  500.     /* fixed alignment fault in case when cs_end is odd. */
  501.     dnCS = (u16)((cs_end[1]<<8) + cs_end[0]);
  502.     //dnCS = *(u16 *)cs_end;

  504.     if (checkSum == dnCS)
  505.     {
  506.         printf("\nChecksum O.K.\n");
  507.     }
  508.     else
  509.     {
  510.         printf("\nChecksum Value => MEM:%x DNW:%x\n",checkSum,dnCS);
  511.         printf("Checksum failed.\n\n");
  512.     }

  514. }

  516. void s3c_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
  517. {
  518.     if(type == EP_TYPE_CONTROL)
  519.     {
  520.         writel((pktcnt<<19)|(xfersize<<0), S5P_OTG_DIEPTSIZ0);
  521.     }
  522.     else if(type == EP_TYPE_BULK)
  523.     {
  524.         writel((1<<29)|(pktcnt<<19)|(xfersize<<0), S5P_OTG_DIEPTSIZ_IN);
  525.     }
  526. }

  528. void s3c_usb_set_outep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
  529. {
  530.     if(type == EP_TYPE_CONTROL)
  531.     {
  532.         writel((1<<29)|(pktcnt<<19)|(xfersize<<0), S5P_OTG_DOEPTSIZ0);
  533.     }
  534.     else if(type == EP_TYPE_BULK)
  535.     {
  536.         writel((pktcnt<<19)|(xfersize<<0), S5P_OTG_DOEPTSIZ_OUT);
  537.     }
  538. }

  540. void s3c_usb_write_ep0_fifo(u8 *buf, int num)
  541. {
  542.     int i;
  543.     u32 Wr_Data=0;

  545.     DBG_SETUP1("[s3c_usb_write_ep0_fifo:");

  547.     for(i=0;i<num;i+=4)
  548.     {
  549.         Wr_Data = ((*(buf+3))<<24)|((*(buf+2))<<16)|((*(buf+1))<<8)|*buf;
  550.         DBG_SETUP2(" 0x%08x,", Wr_Data);
  551.         writel(Wr_Data, S5P_OTG_EP0_FIFO);
  552.         buf += 4;
  553.     }

  555.     DBG_SETUP2("]\n");
  556. }


  559. void s3c_usb_write_in_fifo(u8 *buf, int num)
  560. {
  561.     int i;
  562.     u32 data=0;

  564.     for(i=0;i<num;i+=4)
  565.     {
  566.         data=((*(buf+3))<<24)|((*(buf+2))<<16)|((*(buf+1))<<8)|*buf;
  567.         writel(data, S5P_OTG_IN_FIFO);
  568.         buf += 4;
  569.     }
  570. }

  572. void s3c_usb_read_out_fifo(u8 *buf, int num)
  573. {
  574.     int i;
  575.     u32 data;

  577.     for (i=0;i<num;i+=4)
  578.     {
  579.         data = readl(S5P_OTG_OUT_FIFO);

  581.         buf[i] = (u8)data;
  582.         buf[i+1] = (u8)(data>>8);
  583.         buf[i+2] = (u8)(data>>16);
  584.         buf[i+3] = (u8)(data>>24);
  585.     }
  586. }

  588. void s3c_usb_get_desc(void)
  589. {
  590.     switch (otg.dev_req.wValue_H) {
  591.     case DEVICE_DESCRIPTOR:
  592.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  593.             otg.dev_req.wLength_L);
  594.         DBG_SETUP1("DEVICE_DESCRIPTOR = 0x%x \n",otg.req_length);
  595.         otg.ep0_state = EP0_STATE_GD_DEV_0;
  596.         break;

  598.     case CONFIGURATION_DESCRIPTOR:
  599.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  600.             otg.dev_req.wLength_L);
  601.         DBG_SETUP1("CONFIGURATION_DESCRIPTOR = 0x%x \n",otg.req_length);

  603.         /* GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 */
  604.         if (otg.req_length > CONFIG_DESC_SIZE){
  605.             otg.ep0_state = EP0_STATE_GD_CFG_0;
  606.         } else
  607.             otg.ep0_state = EP0_STATE_GD_CFG_ONLY_0;
  608.         break;

  610.     case STRING_DESCRIPTOR :
  611.         DBG_SETUP1("STRING_DESCRIPTOR \n");

  613.         switch(otg.dev_req.wValue_L) {
  614.         case 0:
  615.             otg.ep0_state = EP0_STATE_GD_STR_I0;
  616.             break;
  617.         case 1:
  618.             otg.ep0_state = EP0_STATE_GD_STR_I1;
  619.             break;
  620.         case 2:
  621.             otg.ep0_state = EP0_STATE_GD_STR_I2;
  622.             break;
  623.         default:
  624.             break;
  625.         }
  626.         break;

  628.     case ENDPOINT_DESCRIPTOR:
  629.         DBG_SETUP1("ENDPOINT_DESCRIPTOR \n");
  630.         switch(otg.dev_req.wValue_L&0xf) {
  631.         case 0:
  632.             otg.ep0_state=EP0_STATE_GD_EP0_ONLY_0;
  633.             break;
  634.         case 1:
  635.             otg.ep0_state=EP0_STATE_GD_EP1_ONLY_0;
  636.             break;
  637.         default:
  638.             break;
  639.         }
  640.         break;

  642.     case DEVICE_QUALIFIER:
  643.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  644.             otg.dev_req.wLength_L);
  645.         DBG_SETUP1("DEVICE_QUALIFIER = 0x%x \n",otg.req_length);
  646.         otg.ep0_state = EP0_STATE_GD_DEV_QUALIFIER;
  647.         break;

  649.     case OTHER_SPEED_CONFIGURATION :
  650.         DBG_SETUP1("OTHER_SPEED_CONFIGURATION \n");
  651.         otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
  652.             otg.dev_req.wLength_L);
  653.         otg.ep0_state = EP0_STATE_GD_OTHER_SPEED;
  654.         break;

  656.     }
  657. }

  659. void s3c_usb_clear_feature(void)
  660. {
  661.     switch (otg.dev_req.bmRequestType) {
  662.     case DEVICE_RECIPIENT:
  663.         DBG_SETUP1("DEVICE_RECIPIENT \n");
  664.         if (otg.dev_req.wValue_L == 1)
  665.             remode_wakeup = FALSE;
  666.         break;

  668.     case ENDPOINT_RECIPIENT:
  669.         DBG_SETUP1("ENDPOINT_RECIPIENT \n");
  670.         if (otg.dev_req.wValue_L == 0) {
  671.             if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
  672.                 get_status.ep_ctrl= 0;

  674.             /* IN    Endpoint */
  675.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
  676.                 get_status.ep_in= 0;

  678.             /* OUT Endpoint */
  679.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
  680.                 get_status.ep_out= 0;
  681.         }
  682.         break;

  684.     default:
  685.         DBG_SETUP1("\n");
  686.         break;
  687.     }
  688.     otg.ep0_state = EP0_STATE_INIT;

  690. }

  692. void s3c_usb_set_feature(void)
  693. {
  694.     u32 tmp;

  696.     switch (otg.dev_req.bmRequestType) {
  697.     case DEVICE_RECIPIENT:
  698.         DBG_SETUP1("DEVICE_RECIPIENT \n");
  699.         if (otg.dev_req.wValue_L == 1)
  700.             remode_wakeup = TRUE;
  701.             break;

  703.     case ENDPOINT_RECIPIENT:
  704.         DBG_SETUP1("ENDPOINT_RECIPIENT \n");
  705.         if (otg.dev_req.wValue_L == 0) {
  706.             if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
  707.                 get_status.ep_ctrl= 1;

  709.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
  710.                 get_status.ep_in= 1;

  712.             if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
  713.                 get_status.ep_out= 1;
  714.         }
  715.         break;

  717.     default:
  718.         DBG_SETUP1("\n");
  719.         break;
  720.     }

  722.     switch (otg.dev_req.wValue_L) {
  723.     case EP_STALL:
  724.         /* TBD: additional processing if required */
  725.         break;

  727.     case TEST_MODE:
  728.         if ((0 != otg.dev_req.wIndex_L ) ||(0 != otg.dev_req.bmRequestType))
  729.             break;

  731.         /* Set TEST MODE*/
  732.         tmp = readl(S5P_OTG_DCTL);
  733.         tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_FORCE_ENABLE_MODE);
  734.         writel(tmp, S5P_OTG_DCTL);

  736.         switch(otg.dev_req.wIndex_H) {
  737.         case TEST_J:
  738.             /*Set Test J*/
  739.             tmp = readl(S5P_OTG_DCTL);
  740.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_J_MODE);
  741.             writel(tmp, S5P_OTG_DCTL);
  742.             break;

  744.         case TEST_K:
  745.             /*Set Test K*/
  746.             tmp = readl(S5P_OTG_DCTL);
  747.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_K_MODE);
  748.             writel(tmp, S5P_OTG_DCTL);
  749.             break;

  751.         case TEST_SE0_NAK:
  752.             /*Set Test SE0NAK*/
  753.             tmp = readl(S5P_OTG_DCTL);
  754.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_SE0_NAK_MODE);
  755.             writel(tmp, S5P_OTG_DCTL);
  756.             break;

  758.         case TEST_PACKET:
  759.             DBG_SETUP1 ("Test_packet\n");
  760.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  761.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, TEST_PKT_SIZE);
  762.             s3c_usb_write_ep0_fifo(test_pkt, TEST_PKT_SIZE);
  763.             tmp = readl(S5P_OTG_DCTL);
  764.             tmp = (tmp & ~(TEST_CONTROL_FIELD)) | (TEST_PACKET_MODE);
  765.             writel(tmp, S5P_OTG_DCTL);
  766.             DBG_SETUP1 ("S5P_OTG_DCTL=0x%08x\n", tmp);
  767.             break;
  768.         }
  769.         break;

  771.     default:
  772.         break;
  773.     }
  774.     otg.ep0_state = EP0_STATE_INIT;

  776. }

  778. void s3c_usb_get_status(void)
  779. {
  780.     switch(otg.dev_req.bmRequestType) {
  781.     case (0x80):    /*device */
  782.         DBG_SETUP1("DEVICE\n");
  783.         get_status.Device=((u8)remode_wakeup<<1)|0x1; /* SelfPowered */
  784.         otg.ep0_state = EP0_STATE_GET_STATUS0;
  785.         break;

  787.     case (0x81):    /*interface */
  788.         DBG_SETUP1("INTERFACE\n");
  789.         get_status.Interface=0;
  790.         otg.ep0_state = EP0_STATE_GET_STATUS1;
  791.         break;

  793.     case (0x82):    /*endpoint */
  794.         DBG_SETUP1("ENDPOINT\n");
  795.         if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
  796.             otg.ep0_state = EP0_STATE_GET_STATUS2;

  798.         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
  799.             otg.ep0_state = EP0_STATE_GET_STATUS3;

  801.         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
  802.             otg.ep0_state = EP0_STATE_GET_STATUS4;
  803.         break;

  805.     default:
  806.         DBG_SETUP1("\n");
  807.         break;
  808.     }

  810. }

  812. void s3c_usb_ep0_int_hndlr(void)
  813. {
  814.     u16 i;
  815.     u32 buf[2]={0x0000, };
  816.     u16 addr;

  818.     DBG_SETUP0("Event EP0\n");

  820.     if (otg.ep0_state == EP0_STATE_INIT) {

  822.         for(i=0;i<2;i++)
  823.             buf[i] = readl(S5P_OTG_EP0_FIFO);

  825.         otg.dev_req.bmRequestType = buf[0];
  826.         otg.dev_req.bRequest    = buf[0]>>8;
  827.         otg.dev_req.wValue_L    = buf[0]>>16;
  828.         otg.dev_req.wValue_H    = buf[0]>>24;
  829.         otg.dev_req.wIndex_L    = buf[1];
  830.         otg.dev_req.wIndex_H    = buf[1]>>8;
  831.         otg.dev_req.wLength_L    = buf[1]>>16;
  832.         otg.dev_req.wLength_H    = buf[1]>>24;

  834. #ifdef USB_OTG_DEBUG_SETUP
  835.         s3c_usb_print_pkt((u8 *)&otg.dev_req, 8);
  836. #endif

  838.         switch (otg.dev_req.bRequest) {
  839.         case STANDARD_SET_ADDRESS:
  840.             /* Set Address Update bit */
  841.             addr = (otg.dev_req.wValue_L);
  842.             writel(1<<18|addr<<4|otg.speed<<0, S5P_OTG_DCFG);
  843.             DBG_SETUP1("S5P_OTG_DCFG : %x, STANDARD_SET_ADDRESS : %d\n",
  844.                     readl(S5P_OTG_DCFG), addr);
  845.             otg.ep0_state = EP0_STATE_INIT;
  846.             break;

  848.         case STANDARD_SET_DESCRIPTOR:
  849.             DBG_SETUP1("STANDARD_SET_DESCRIPTOR \n");
  850.             break;

  852.         case STANDARD_SET_CONFIGURATION:
  853.             DBG_SETUP1("STANDARD_SET_CONFIGURATION \n");
  854.             /* Configuration value in configuration descriptor */
  855.             config_value = otg.dev_req.wValue_L;
  856.             otg.set_config = 1;
  857.             otg.ep0_state = EP0_STATE_INIT;
  858.             break;

  860.         case STANDARD_GET_CONFIGURATION:
  861.             DBG_SETUP1("STANDARD_GET_CONFIGURATION \n");
  862.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);

  864.             /*ep0 enable, clear nak, next ep0, 8byte */
  865.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  866.             writel(config_value, S5P_OTG_EP0_FIFO);
  867.             otg.ep0_state = EP0_STATE_INIT;
  868.             break;

  870.         case STANDARD_GET_DESCRIPTOR:
  871.             DBG_SETUP1("STANDARD_GET_DESCRIPTOR :");
  872.             s3c_usb_get_desc();
  873.             break;

  875.         case STANDARD_CLEAR_FEATURE:
  876.             DBG_SETUP1("STANDARD_CLEAR_FEATURE :");
  877.             s3c_usb_clear_feature();
  878.             break;

  880.         case STANDARD_SET_FEATURE:
  881.             DBG_SETUP1("STANDARD_SET_FEATURE :");
  882.             s3c_usb_set_feature();
  883.             break;

  885.         case STANDARD_GET_STATUS:
  886.             DBG_SETUP1("STANDARD_GET_STATUS :");
  887.             s3c_usb_get_status();
  888.             break;

  890.         case STANDARD_GET_INTERFACE:
  891.             DBG_SETUP1("STANDARD_GET_INTERFACE \n");
  892.             otg.ep0_state = EP0_STATE_INTERFACE_GET;
  893.             break;

  895.         case STANDARD_SET_INTERFACE:
  896.             DBG_SETUP1("STANDARD_SET_INTERFACE \n");
  897.             get_intf.AlternateSetting= otg.dev_req.wValue_L;
  898.             otg.ep0_state = EP0_STATE_INIT;
  899.             break;

  901.         case STANDARD_SYNCH_FRAME:
  902.             DBG_SETUP1("STANDARD_SYNCH_FRAME \n");
  903.             otg.ep0_state = EP0_STATE_INIT;
  904.             break;

  906.         default:
  907.             break;
  908.         }
  909.     }

  911.     s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.ctrl_max_pktsize);

  913.     if(otg.speed == USB_HIGH) {
  914.         /*clear nak, next ep0, 64byte */
  915.         writel(((1<<26)|(CONTROL_EP<<11)|(0<<0)), S5P_OTG_DIEPCTL0);
  916.     }
  917.     else {
  918.         /*clear nak, next ep0, 8byte */
  919.         writel(((1<<26)|(CONTROL_EP<<11)|(3<<0)), S5P_OTG_DIEPCTL0);
  920.     }

  922. }

  924. void s3c_usb_set_otherspeed_conf_desc(u32 length)
  925. {
  926.     /* Standard device descriptor */
  927.     if (otg.speed == USB_HIGH)
  928.     {
  929.      if (length ==9)
  930.      {
  931.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 9);
  932.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  933.             s3c_usb_write_ep0_fifo(((u8 *)&config_full)+0, 9);
  934.         }
  935.      else if(length ==32)
  936.         {
  937.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 32);
  938.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  939.             s3c_usb_write_ep0_fifo(((u8 *)&config_full_total)+0, 32);

  941.      }
  942.         otg.ep0_state = EP0_STATE_INIT;
  943.     }
  944.     else
  945.     {
  946.      if (length ==9)
  947.      {
  948.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  949.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  950.             s3c_usb_write_ep0_fifo(((u8 *)&config_high)+0, 8);
  951.         }
  952.      else if(length ==32)
  953.         {
  954.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  955.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  956.             s3c_usb_write_ep0_fifo(((u8 *)&config_high_total)+0, 8);
  957.      }
  958.         otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_1;
  959.     }
  960. }

  962. void s3c_usb_transfer_ep0(void)
  963. {

  965.     DBG_SETUP0("otg.ep0_state = %d\n", otg.ep0_state);

  967.     switch (otg.ep0_state) {
  968.     case EP0_STATE_INIT:
  969.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 0);

  971.         /*ep0 enable, clear nak, next ep0, 8byte */
  972.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  973.         DBG_SETUP1("EP0_STATE_INIT\n");
  974.         break;

  976.     /* GET_DESCRIPTOR:DEVICE */
  977.     case EP0_STATE_GD_DEV_0:
  978.         DBG_SETUP1("EP0_STATE_GD_DEV_0 :");
  979.         if (otg.speed == USB_HIGH) {
  980.             DBG_SETUP1("High Speed\n");

  982.             /*ep0 enable, clear nak, next ep0, max 64byte */
  983.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  984.             if (otg.req_length < DEVICE_DESC_SIZE) {
  985.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  986.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, otg.req_length);
  987.             } else {
  988.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, DEVICE_DESC_SIZE);
  989.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, DEVICE_DESC_SIZE);
  990.             }
  991.             otg.ep0_state = EP0_STATE_INIT;
  992.         } else {
  993.             DBG_SETUP1("Full Speed\n");
  994.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  995.             if(otg.req_length<DEVICE_DESC_SIZE) {
  996.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  997.             } else {
  998.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, DEVICE_DESC_SIZE);
  999.             }

  1001.             if(otg.req_length<FS_CTRL_PKT_SIZE) {
  1002.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, otg.req_length);
  1003.                 otg.ep0_state = EP0_STATE_INIT;
  1004.             } else {
  1005.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+0, FS_CTRL_PKT_SIZE);
  1006.                 otg.ep0_state = EP0_STATE_GD_DEV_1;
  1007.             }
  1008.         }
  1009.         break;

  1011.     case EP0_STATE_GD_DEV_1:
  1012.         DBG_SETUP1("EP0_STATE_GD_DEV_1\n");
  1013.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1014.         if(otg.req_length<(2*FS_CTRL_PKT_SIZE)) {
  1015.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+FS_CTRL_PKT_SIZE,
  1016.                         (otg.req_length-FS_CTRL_PKT_SIZE));
  1017.             otg.ep0_state = EP0_STATE_INIT;
  1018.         } else {
  1019.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+FS_CTRL_PKT_SIZE,
  1020.                         FS_CTRL_PKT_SIZE);
  1021.             otg.ep0_state = EP0_STATE_GD_DEV_2;
  1022.         }
  1023.         break;

  1025.     case EP0_STATE_GD_DEV_2:
  1026.         DBG_SETUP1("EP0_STATE_GD_DEV_2\n");
  1027.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1028.         if(otg.req_length<DEVICE_DESC_SIZE) {
  1029.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+(2*FS_CTRL_PKT_SIZE),
  1030.                         (otg.req_length-2*FS_CTRL_PKT_SIZE));
  1031.         } else {
  1032.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.dev))+(2*FS_CTRL_PKT_SIZE),
  1033.                         (DEVICE_DESC_SIZE-2*FS_CTRL_PKT_SIZE));
  1034.         }
  1035.         otg.ep0_state = EP0_STATE_INIT;
  1036.         break;

  1038.     /* GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 */
  1039.     case EP0_STATE_GD_CFG_0:
  1040.         DBG_SETUP1("EP0_STATE_GD_CFG_0 :");
  1041.         if (otg.speed == USB_HIGH)
  1042.         {
  1043.             DBG_SETUP1("High Speed\n");
  1044.             writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1045.             if(otg.req_length<CONFIG_DESC_TOTAL_SIZE)
  1046.             {
  1047.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1048.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1049.             }
  1050.             else
  1051.             {
  1052.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_TOTAL_SIZE);
  1053.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, CONFIG_DESC_TOTAL_SIZE);
  1054.             }
  1055.             otg.ep0_state = EP0_STATE_INIT;
  1056.         }
  1057.         else
  1058.         {
  1059.             DBG_SETUP1("Full Speed\n");
  1060.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1061.             if(otg.req_length<CONFIG_DESC_TOTAL_SIZE)
  1062.             {
  1063.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1064.             }
  1065.             else
  1066.             {
  1067.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_TOTAL_SIZE);
  1068.             }
  1069.             if(otg.req_length<FS_CTRL_PKT_SIZE)
  1070.             {
  1071.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1072.                 otg.ep0_state = EP0_STATE_INIT;
  1073.             }
  1074.             else
  1075.             {
  1076.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, FS_CTRL_PKT_SIZE);
  1077.                 otg.ep0_state = EP0_STATE_GD_CFG_1;
  1078.             }
  1079.         }
  1080.         break;

  1082.     case EP0_STATE_GD_CFG_1:
  1083.         DBG_SETUP1("EP0_STATE_GD_CFG_1\n");
  1084.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1085.         if(otg.req_length<(2*FS_CTRL_PKT_SIZE))
  1086.         {
  1087.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+FS_CTRL_PKT_SIZE,
  1088.                         (otg.req_length-FS_CTRL_PKT_SIZE));
  1089.             otg.ep0_state = EP0_STATE_INIT;
  1090.         }
  1091.         else
  1092.         {
  1093.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+FS_CTRL_PKT_SIZE,
  1094.                         FS_CTRL_PKT_SIZE);
  1095.             otg.ep0_state = EP0_STATE_GD_CFG_2;
  1096.         }
  1097.         break;

  1099.     case EP0_STATE_GD_CFG_2:
  1100.         DBG_SETUP1("EP0_STATE_GD_CFG_2\n");
  1101.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1102.         if(otg.req_length<(3*FS_CTRL_PKT_SIZE))
  1103.         {
  1104.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(2*FS_CTRL_PKT_SIZE),
  1105.                         (otg.req_length-2*FS_CTRL_PKT_SIZE));
  1106.             otg.ep0_state = EP0_STATE_INIT;
  1107.         }
  1108.         else
  1109.         {
  1110.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(2*FS_CTRL_PKT_SIZE),
  1111.                         FS_CTRL_PKT_SIZE);
  1112.             otg.ep0_state = EP0_STATE_GD_CFG_3;
  1113.         }
  1114.         break;

  1116.     case EP0_STATE_GD_CFG_3:
  1117.         DBG_SETUP1("EP0_STATE_GD_CFG_3\n");
  1118.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1119.         if(otg.req_length<(4*FS_CTRL_PKT_SIZE))
  1120.         {
  1121.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(3*FS_CTRL_PKT_SIZE),
  1122.                         (otg.req_length-3*FS_CTRL_PKT_SIZE));
  1123.             otg.ep0_state = EP0_STATE_INIT;
  1124.         }
  1125.         else
  1126.         {
  1127.             s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+(3*FS_CTRL_PKT_SIZE),
  1128.                         FS_CTRL_PKT_SIZE);
  1129.             otg.ep0_state = EP0_STATE_GD_CFG_4;
  1130.         }
  1131.         break;

  1133.     case EP0_STATE_GD_CFG_4:
  1134.         DBG_SETUP1("EP0_STATE_GD_CFG_4\n");
  1135.         otg.ep0_state = EP0_STATE_INIT;
  1136.         break;

  1138.     case EP0_STATE_GD_DEV_QUALIFIER:    /*only supported in USB 2.0*/
  1139.         DBG_SETUP1("EP0_STATE_GD_DEV_QUALIFIER\n");
  1140.         writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1141.         if(otg.req_length<10)
  1142.         {
  1143.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1144.             s3c_usb_write_ep0_fifo((u8 *)qualifier_desc+0, otg.req_length);
  1145.         }
  1146.         else
  1147.         {
  1148.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 10);
  1149.             s3c_usb_write_ep0_fifo((u8 *)qualifier_desc+0, 10);
  1150.         }
  1151.         otg.ep0_state = EP0_STATE_INIT;
  1152.         break;

  1154.     case EP0_STATE_GD_OTHER_SPEED:
  1155.             DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED\n");
  1156.             s3c_usb_set_otherspeed_conf_desc(otg.req_length);
  1157.             break;

  1159.     case EP0_STATE_GD_OTHER_SPEED_HIGH_1:
  1160.         DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED_HIGH_1\n");
  1161.         if(otg.req_length==9)
  1162.         {
  1163.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1164.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1165.                 s3c_usb_write_ep0_fifo(((u8 *)&config_high)+8, 1);
  1166.                 otg.ep0_state = EP0_STATE_INIT;
  1167.         }
  1168.         else
  1169.         {
  1170.             s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  1171.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1172.                 s3c_usb_write_ep0_fifo(((u8 *)&config_high)+8, 8);
  1173.                 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_2;
  1174.         }
  1175.             break;

  1177.     case EP0_STATE_GD_OTHER_SPEED_HIGH_2:
  1178.         DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED_HIGH_2\n");
  1179.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  1180.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1181.             s3c_usb_write_ep0_fifo(((u8 *)&config_high)+16, 8);
  1182.             otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_3;
  1183.             break;

  1185.     case EP0_STATE_GD_OTHER_SPEED_HIGH_3:
  1186.         DBG_SETUP1("EP0_STATE_GD_OTHER_SPEED_HIGH_3\n");
  1187.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
  1188.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1189.             s3c_usb_write_ep0_fifo(((u8 *)&config_high)+24, 8);
  1190.             otg.ep0_state = EP0_STATE_INIT;
  1191.             break;

  1193.     /* GET_DESCRIPTOR:CONFIGURATION ONLY*/
  1194.     case EP0_STATE_GD_CFG_ONLY_0:
  1195.         DBG_SETUP1("EP0_STATE_GD_CFG_ONLY_0:");
  1196.         if (otg.speed == USB_HIGH)
  1197.         {
  1198.             DBG_SETUP1("High Speed\n");
  1199.             if(otg.req_length<CONFIG_DESC_SIZE)
  1200.             {
  1201.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1202.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1203.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1204.             }
  1205.             else
  1206.             {
  1207.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_SIZE);
  1208.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1209.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0,
  1210.                             CONFIG_DESC_SIZE);
  1211.             }
  1212.             otg.ep0_state = EP0_STATE_INIT;
  1213.         }
  1214.         else
  1215.         {
  1216.             DBG_SETUP1("Full Speed\n");
  1217.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1218.             if(otg.req_length<CONFIG_DESC_SIZE)
  1219.             {
  1220.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1221.             }
  1222.             else
  1223.             {
  1224.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, CONFIG_DESC_SIZE);
  1225.             }
  1226.             if(otg.req_length<FS_CTRL_PKT_SIZE)
  1227.             {
  1228.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, otg.req_length);
  1229.                 otg.ep0_state = EP0_STATE_INIT;
  1230.             }
  1231.             else
  1232.             {
  1233.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+0, FS_CTRL_PKT_SIZE);
  1234.                 otg.ep0_state = EP0_STATE_GD_CFG_ONLY_1;
  1235.             }
  1236.         }
  1237.         break;

  1239.     case EP0_STATE_GD_CFG_ONLY_1:
  1240.         DBG_SETUP1("EP0_STATE_GD_CFG_ONLY_1\n");
  1241.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1242.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.config))+FS_CTRL_PKT_SIZE,
  1243.                     (CONFIG_DESC_SIZE-FS_CTRL_PKT_SIZE));
  1244.         otg.ep0_state = EP0_STATE_INIT;
  1245.         break;

  1247.     /* GET_DESCRIPTOR:INTERFACE ONLY */

  1249.     case EP0_STATE_GD_IF_ONLY_0:
  1250.         DBG_SETUP1("EP0_STATE_GD_IF_ONLY_0 :");
  1251.         if (otg.speed == USB_HIGH)
  1252.         {
  1253.             DBG_SETUP1("High Speed\n");
  1254.             if(otg.req_length<INTERFACE_DESC_SIZE)
  1255.             {
  1256.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1257.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1258.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, otg.req_length);
  1259.             }
  1260.             else
  1261.             {
  1262.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, INTERFACE_DESC_SIZE);
  1263.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1264.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, INTERFACE_DESC_SIZE);
  1265.             }
  1266.             otg.ep0_state = EP0_STATE_INIT;
  1267.         }
  1268.         else
  1269.         {
  1270.             DBG_SETUP1("Full Speed\n");
  1271.             writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1272.             if(otg.req_length<INTERFACE_DESC_SIZE)
  1273.             {
  1274.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.req_length);
  1275.             }
  1276.             else
  1277.             {
  1278.                 s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, INTERFACE_DESC_SIZE);
  1279.             }
  1280.             if(otg.req_length<FS_CTRL_PKT_SIZE)
  1281.             {
  1282.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, otg.req_length);
  1283.                 otg.ep0_state = EP0_STATE_INIT;
  1284.             }
  1285.             else
  1286.             {
  1287.                 s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+0, FS_CTRL_PKT_SIZE);
  1288.                 otg.ep0_state = EP0_STATE_GD_IF_ONLY_1;
  1289.             }
  1290.         }
  1291.         break;

  1293.     case EP0_STATE_GD_IF_ONLY_1:
  1294.         DBG_SETUP1("EP0_STATE_GD_IF_ONLY_1\n");
  1295.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1296.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.intf))+FS_CTRL_PKT_SIZE,
  1297.                     (INTERFACE_DESC_SIZE-FS_CTRL_PKT_SIZE));
  1298.         otg.ep0_state = EP0_STATE_INIT;
  1299.         break;


  1302.     /* GET_DESCRIPTOR:ENDPOINT 1 ONLY */
  1303.     case EP0_STATE_GD_EP0_ONLY_0:
  1304.         DBG_SETUP1("EP0_STATE_GD_EP0_ONLY_0\n");
  1305.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1306.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
  1307.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.ep1))+0, ENDPOINT_DESC_SIZE);
  1308.         otg.ep0_state = EP0_STATE_INIT;
  1309.         break;

  1311.     /* GET_DESCRIPTOR:ENDPOINT 2 ONLY */
  1312.     case EP0_STATE_GD_EP1_ONLY_0:
  1313.         DBG_SETUP1("EP0_STATE_GD_EP1_ONLY_0\n");
  1314.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
  1315.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1316.         s3c_usb_write_ep0_fifo(((u8 *)&(otg.desc.ep2))+0, ENDPOINT_DESC_SIZE);
  1317.         otg.ep0_state = EP0_STATE_INIT;
  1318.         break;

  1320.     /* GET_DESCRIPTOR:STRING */
  1321.     case EP0_STATE_GD_STR_I0:
  1322.         DBG_SETUP1("EP0_STATE_GD_STR_I0\n");
  1323.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, STRING_DESC0_SIZE);
  1324.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1325.         s3c_usb_write_ep0_fifo((u8 *)string_desc0, STRING_DESC0_SIZE);
  1326.         otg.ep0_state = EP0_STATE_INIT;
  1327.         break;

  1329.     case EP0_STATE_GD_STR_I1:
  1330.         DBG_SETUP1("EP0_STATE_GD_STR_I1 %d\n", otg.ep0_substate);
  1331.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc1));
  1332.         if ((otg.ep0_substate*otg.ctrl_max_pktsize+otg.ctrl_max_pktsize)
  1333.             < sizeof(string_desc1)) {

  1335.             if (otg.speed == USB_HIGH)
  1336.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1337.             else
  1338.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1339.             s3c_usb_write_ep0_fifo((u8 *)string_desc1+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1340.                         otg.ctrl_max_pktsize);
  1341.             otg.ep0_state = EP0_STATE_GD_STR_I1;
  1342.             otg.ep0_substate++;
  1343.         } else {
  1344.             if (otg.speed == USB_HIGH)
  1345.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1346.             else
  1347.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1348.             s3c_usb_write_ep0_fifo((u8 *)string_desc1+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1349.                         sizeof(string_desc1)-(otg.ep0_substate*otg.ctrl_max_pktsize));
  1350.             otg.ep0_state = EP0_STATE_INIT;
  1351.             otg.ep0_substate = 0;
  1352.         }
  1353.         break;

  1355.     case EP0_STATE_GD_STR_I2:
  1356.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc2));
  1357.         if ((otg.ep0_substate*otg.ctrl_max_pktsize+otg.ctrl_max_pktsize)
  1358.             < sizeof(string_desc2)) {

  1360.             if (otg.speed == USB_HIGH)
  1361.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1362.             else
  1363.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1364.             s3c_usb_write_ep0_fifo((u8 *)string_desc2+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1365.                         otg.ctrl_max_pktsize);
  1366.             otg.ep0_state = EP0_STATE_GD_STR_I2;
  1367.             otg.ep0_substate++;
  1368.         } else {
  1369.             if (otg.speed == USB_HIGH)
  1370.                 writel(EPEN_CNAK_EP0_64, S5P_OTG_DIEPCTL0);
  1371.             else
  1372.                 writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1373.             s3c_usb_write_ep0_fifo((u8 *)string_desc2+(otg.ep0_substate*otg.ctrl_max_pktsize),
  1374.                         sizeof(string_desc2)-(otg.ep0_substate*otg.ctrl_max_pktsize));
  1375.             otg.ep0_state = EP0_STATE_INIT;
  1376.             otg.ep0_substate = 0;
  1377.         }
  1378.         DBG_SETUP1("EP0_STATE_GD_STR_I2 %d", otg.ep0_substate);
  1379.         break;

  1381.     case EP0_STATE_INTERFACE_GET:
  1382.         DBG_SETUP1("EP0_STATE_INTERFACE_GET\n");
  1383.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1384.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1385.         s3c_usb_write_ep0_fifo((u8 *)&get_intf+0, 1);
  1386.         otg.ep0_state = EP0_STATE_INIT;
  1387.         break;


  1390.     case EP0_STATE_GET_STATUS0:
  1391.         DBG_SETUP1("EP0_STATE_GET_STATUS0\n");
  1392.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1393.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1394.         s3c_usb_write_ep0_fifo((u8 *)&get_status+0, 1);
  1395.         otg.ep0_state = EP0_STATE_INIT;
  1396.         break;

  1398.     case EP0_STATE_GET_STATUS1:
  1399.         DBG_SETUP1("EP0_STATE_GET_STATUS1\n");
  1400.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1401.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1402.         s3c_usb_write_ep0_fifo((u8 *)&get_status+1, 1);
  1403.         otg.ep0_state = EP0_STATE_INIT;
  1404.         break;

  1406.     case EP0_STATE_GET_STATUS2:
  1407.         DBG_SETUP1("EP0_STATE_GET_STATUS2\n");
  1408.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1409.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1410.         s3c_usb_write_ep0_fifo((u8 *)&get_status+2, 1);
  1411.         otg.ep0_state = EP0_STATE_INIT;
  1412.         break;

  1414.     case EP0_STATE_GET_STATUS3:
  1415.         DBG_SETUP1("EP0_STATE_GET_STATUS3\n");
  1416.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1417.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1418.         s3c_usb_write_ep0_fifo((u8 *)&get_status+3, 1);
  1419.         otg.ep0_state = EP0_STATE_INIT;
  1420.         break;

  1422.     case EP0_STATE_GET_STATUS4:
  1423.         DBG_SETUP1("EP0_STATE_GET_STATUS4\n");
  1424.         s3c_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
  1425.         writel(EPEN_CNAK_EP0_8, S5P_OTG_DIEPCTL0);
  1426.         s3c_usb_write_ep0_fifo((u8 *)&get_status+4, 1);
  1427.         otg.ep0_state = EP0_STATE_INIT;
  1428.         break;

  1430.     default:
  1431.         break;
  1432.     }
  1433. }


  1436. void s3c_usb_int_bulkin(void)
  1437. {
  1438.     u8* bulkin_buf;
  1439.     u32 remain_cnt;

  1441.     DBG_BULK0("Bulk In Function\n");

  1443.     bulkin_buf = (u8*)otg.up_ptr;
  1444.     remain_cnt = otg.up_size- ((u32)otg.up_ptr - otg.up_addr);
  1445.     DBG_BULK1("bulkin_buf = 0x%x,remain_cnt = 0x%x \n", bulkin_buf, remain_cnt);

  1447.     if (remain_cnt > otg.bulkin_max_pktsize) {
  1448.         s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, otg.bulkin_max_pktsize);

  1450.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1451.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1452.             S5P_OTG_DIEPCTL_IN);

  1454.         s3c_usb_write_in_fifo(bulkin_buf, otg.bulkin_max_pktsize);

  1456.         otg.up_ptr += otg.bulkin_max_pktsize;

  1458.     } else if(remain_cnt > 0) {
  1459.         s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, remain_cnt);

  1461.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1462.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1463.             S5P_OTG_DIEPCTL_IN);

  1465.         s3c_usb_write_in_fifo(bulkin_buf, remain_cnt);

  1467.         otg.up_ptr += remain_cnt;

  1469.     } else { /*remain_cnt = 0*/
  1470.         writel((DEPCTL_SNAK|DEPCTL_BULK_TYPE), S5P_OTG_DIEPCTL_IN);
  1471.     }
  1472. }

  1474. void s3c_usb_upload_start(void)
  1475. {
  1476.     u8 tmp_buf[12];
  1477.     u32 check;

  1479.     s3c_usb_read_out_fifo((u8 *)tmp_buf, 10);
  1480.     check = *((u8 *)(tmp_buf+8)) + (*((u8 *)(tmp_buf+9))<<8);

  1482.     if (check==0x1) {
  1483.         otg.up_addr =
  1484.             *((u8 *)(tmp_buf+0))+
  1485.             (*((u8 *)(tmp_buf+1))<<8)+
  1486.             (*((u8 *)(tmp_buf+2))<<16)+
  1487.             (*((u8 *)(tmp_buf+3))<<24);

  1489.         otg.up_size =
  1490.             *((u8 *)(tmp_buf+4))+
  1491.             (*((u8 *)(tmp_buf+5))<<8)+
  1492.             (*((u8 *)(tmp_buf+6))<<16)+
  1493.             (*((u8 *)(tmp_buf+7))<<24);

  1495.         otg.up_ptr=(u8 *)otg.up_addr;
  1496.         DBG_BULK1("UploadAddress : 0x%x, UploadSize: %d\n",
  1497.             otg.up_addr, otg.up_size);

  1499.         if (otg.op_mode == USB_CPU) {
  1500.             if (otg.up_size > otg.bulkin_max_pktsize) {
  1501.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
  1502.                     otg.bulkin_max_pktsize);
  1503.             } else {
  1504.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
  1505.                     otg.up_size);
  1506.             }

  1508.             /*ep1 enable, clear nak, bulk, usb active, max pkt 64*/
  1509.             writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1510.                 S5P_OTG_DIEPCTL_IN);
  1511.         } else if ((otg.op_mode == USB_DMA) && (otg.up_size > 0)) {
  1512.             u32 pktcnt, remainder;

  1514.             DBG_BULK1("Dma Start for IN PKT \n");

  1516.             writel(MODE_DMA|BURST_INCR4|GBL_INT_UNMASK,
  1517.                 S5P_OTG_GAHBCFG);
  1518.             writel(INT_RESUME|INT_OUT_EP|INT_IN_EP| INT_ENUMDONE|
  1519.                 INT_RESET|INT_SUSPEND, S5P_OTG_GINTMSK);

  1521.             writel((u32)otg.up_ptr, S5P_OTG_DIEPDMA_IN);

  1523.             pktcnt = (u32)(otg.up_size/otg.bulkin_max_pktsize);
  1524.             remainder = (u32)(otg.up_size%otg.bulkin_max_pktsize);
  1525.             if(remainder != 0) {
  1526.                 pktcnt += 1;
  1527.             }

  1529.             if (pktcnt > 1023) {
  1530.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
  1531.                     (otg.bulkin_max_pktsize*1023));
  1532.             } else {
  1533.                 s3c_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
  1534.                     otg.up_size);
  1535.             }

  1537.             /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
  1538.             writel(1u<<31|1<<26|2<<18|1<<15|BULK_IN_EP<<11|
  1539.                 otg.bulkin_max_pktsize<<0,
  1540.                 S5P_OTG_DIEPCTL_IN);
  1541.         }
  1542.     }
  1543.     otg.dn_filesize=0;
  1544. }

  1546. void s3c_usb_download_start(u32 fifo_cnt_byte)
  1547. {
  1548.     u8 tmp_buf[8];

  1550.     s3c_usb_read_out_fifo((u8 *)tmp_buf, 8);
  1551.     DBG_BULK1("downloadFileSize==0, 1'st BYTE_READ_CNT_REG : %x\n",
  1552.         fifo_cnt_byte);

  1554.     otg.dn_addr=s3c_usbd_dn_addr;
  1555.     otg.dn_filesize=
  1556.         *((u8 *)(tmp_buf+4))+
  1557.         (*((u8 *)(tmp_buf+5))<<8)+
  1558.         (*((u8 *)(tmp_buf+6))<<16)+
  1559.         (*((u8 *)(tmp_buf+7))<<24);

  1561.     otg.dn_ptr=(u8 *)otg.dn_addr;
  1562.     DBG_BULK1("downloadAddress : 0x%x, downloadFileSize: %x\n",
  1563.         otg.dn_addr, otg.dn_filesize);

  1565.     /* The first 8-bytes are deleted.*/
  1566.     s3c_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte-8);
  1567.     otg.dn_ptr += fifo_cnt_byte-8;

  1569.     if (otg.op_mode == USB_CPU) {
  1570.         s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1,
  1571.             otg.bulkout_max_pktsize);

  1573.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1574.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1575.         S5P_OTG_DOEPCTL_OUT);
  1576.     } else if (otg.dn_filesize>otg.bulkout_max_pktsize) {
  1577.         u32 pkt_cnt, remain_cnt;

  1579.         DBG_BULK1("downloadFileSize!=0, Dma Start for 2nd OUT PKT \n");
  1580.         writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  1581.             INT_RESET|INT_SUSPEND, S5P_OTG_GINTMSK); /*gint unmask */
  1582.         writel(MODE_DMA|BURST_INCR4|GBL_INT_UNMASK,
  1583.             S5P_OTG_GAHBCFG);
  1584.         writel((u32)otg.dn_ptr, S5P_OTG_DOEPDMA_OUT);
  1585.         pkt_cnt = (u32)(otg.dn_filesize-otg.bulkout_max_pktsize)/otg.bulkout_max_pktsize;
  1586.         remain_cnt = (u32)((otg.dn_filesize-otg.bulkout_max_pktsize)%otg.bulkout_max_pktsize);
  1587.         if(remain_cnt != 0) {
  1588.             pkt_cnt += 1;
  1589.         }

  1591.         if (pkt_cnt > 1023) {
  1592.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
  1593.                 (otg.bulkout_max_pktsize*1023));
  1594.         } else {
  1595.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, pkt_cnt,
  1596.                 (otg.dn_filesize-otg.bulkout_max_pktsize));
  1597.         }

  1599.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1600.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1601.             S5P_OTG_DOEPCTL_OUT);
  1602.     }
  1603. }

  1605. void s3c_usb_download_continue(u32 fifo_cnt_byte)
  1606. {
  1607.     if (otg.op_mode == USB_CPU) {
  1608.         s3c_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte);
  1609.         otg.dn_ptr += fifo_cnt_byte;
  1610.         DBG_BULK1("downloadFileSize!=0, 2nd BYTE_READ_CNT_REG = 0x%x, m_pDownPt = 0x%x\n",
  1611.                 fifo_cnt_byte, otg.dn_ptr);

  1613.         s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);

  1615.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1616.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1617.             S5P_OTG_DOEPCTL_OUT);

  1619.         /* USB format : addr(4)+size(4)+data(n)+cs(2) */
  1620.         if (((u32)otg.dn_ptr - otg.dn_addr) >= (otg.dn_filesize - 8)) {
  1621.             printf("Download Done!! Download Address: 0x%x, Download Filesize:0x%x\n",
  1622.                 otg.dn_addr, (otg.dn_filesize-10));

  1624.             s3c_usbd_dn_cnt     = otg.dn_filesize-10;
  1625.             s3c_usbd_dn_addr    = otg.dn_addr;

  1627. #ifdef USB_CHECKSUM_EN
  1628.             s3c_usb_verify_checksum();
  1629. #endif
  1630.             s3c_receive_done = 1;
  1631.         }

  1633.     }\
  1634. }

  1636. void s3c_usb_int_bulkout(u32 fifo_cnt_byte)
  1637. {
  1638.     DBG_BULK0("Bulk Out Function : otg.dn_filesize=0x%x\n", otg.dn_filesize);
  1639.     if (otg.dn_filesize==0) {
  1640.         if (fifo_cnt_byte == 10) {
  1641.             s3c_usb_upload_start();
  1642.         } else {
  1643.             s3c_usb_download_start(fifo_cnt_byte);
  1644.         }
  1645.     } else {
  1646.         s3c_usb_download_continue(fifo_cnt_byte);
  1647.     }
  1648. }

  1650. void s3c_usb_dma_in_done(void)
  1651. {
  1652.     s32 remain_cnt;

  1654.     DBG_BULK0("DMA IN : Transfer Done\n");

  1656.     otg.up_ptr = (u8 *)readl(S5P_OTG_DIEPDMA_IN);
  1657.     remain_cnt = otg.up_size- ((u32)otg.up_ptr - otg.up_addr);

  1659.     if (remain_cnt>0) {
  1660.         u32 pktcnt, remainder;
  1661.         pktcnt = (u32)(remain_cnt/otg.bulkin_max_pktsize);
  1662.         remainder = (u32)(remain_cnt%otg.bulkin_max_pktsize);
  1663.         if(remainder != 0) {
  1664.             pktcnt += 1;
  1665.         }
  1666.         DBG_SETUP1("remain_cnt : %d \n", remain_cnt);
  1667.         if (pktcnt> 1023) {
  1668.             s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
  1669.                 (otg.bulkin_max_pktsize*1023));
  1670.         } else {
  1671.             s3c_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
  1672.                 remain_cnt);
  1673.         }

  1675.         /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
  1676.         writel(1u<<31|1<<26|2<<18|1<<15|BULK_IN_EP<<11|otg.bulkin_max_pktsize<<0,
  1677.             S5P_OTG_DIEPCTL_IN);
  1678.     } else
  1679.         DBG_SETUP1("DMA IN : Transfer Complete\n");
  1680. }

  1682. void s3c_usb_dma_out_done(void)
  1683. {
  1684.     s32 remain_cnt;

  1686.     DBG_BULK1("DMA OUT : Transfer Done\n");
  1687.     otg.dn_ptr = (u8 *)readl(S5P_OTG_DOEPDMA_OUT);

  1689.     remain_cnt = otg.dn_filesize - ((u32)otg.dn_ptr - otg.dn_addr + 8);

  1691.     if (remain_cnt>0) {
  1692.         u32 pktcnt, remainder;
  1693.         pktcnt = (u32)(remain_cnt/otg.bulkout_max_pktsize);
  1694.         remainder = (u32)(remain_cnt%otg.bulkout_max_pktsize);
  1695.         if(remainder != 0) {
  1696.             pktcnt += 1;
  1697.         }
  1698.         DBG_BULK1("remain_cnt : %d \n", remain_cnt);
  1699.         if (pktcnt> 1023) {
  1700.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
  1701.                 (otg.bulkout_max_pktsize*1023));
  1702.         } else {
  1703.             s3c_usb_set_outep_xfersize(EP_TYPE_BULK, pktcnt,
  1704.                 remain_cnt);
  1705.         }

  1707.         /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64*/
  1708.         writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1709.             S5P_OTG_DOEPCTL_OUT);
  1710.     } else {
  1711.         DBG_BULK1("DMA OUT : Transfer Complete\n");
  1712.         udelay(500);        /*for FPGA ???*/
  1713.     }
  1714. }

  1716. void s3c_usb_set_all_outep_nak(void)
  1717. {
  1718.     u8 i;
  1719.     u32 tmp;

  1721.     for(i=0;i<16;i++)
  1722.     {
  1723.         tmp = readl(S5P_OTG_DOEPCTL0+0x20*i);
  1724.         tmp |= DEPCTL_SNAK;
  1725.         writel(tmp, S5P_OTG_DOEPCTL0+0x20*i);
  1726.     }
  1727. }

  1729. void s3c_usb_clear_all_outep_nak(void)
  1730. {
  1731.     u8 i;
  1732.     u32 tmp;

  1734.     for(i=0;i<16;i++)
  1735.     {
  1736.         tmp = readl(S5P_OTG_DOEPCTL0+0x20*i);
  1737.         tmp |= (DEPCTL_EPENA|DEPCTL_CNAK);
  1738.         writel(tmp, S5P_OTG_DOEPCTL0+0x20*i);
  1739.     }
  1740. }

  1742. void s3c_usb_set_max_pktsize(USB_SPEED speed)
  1743. {
  1744.     if (speed == USB_HIGH)
  1745.     {
  1746.         otg.speed = USB_HIGH;
  1747.         otg.ctrl_max_pktsize = HS_CTRL_PKT_SIZE;
  1748.         otg.bulkin_max_pktsize = HS_BULK_PKT_SIZE;
  1749.         otg.bulkout_max_pktsize = HS_BULK_PKT_SIZE;
  1750.     }
  1751.     else
  1752.     {
  1753.         otg.speed = USB_FULL;
  1754.         otg.ctrl_max_pktsize = FS_CTRL_PKT_SIZE;
  1755.         otg.bulkin_max_pktsize = FS_BULK_PKT_SIZE;
  1756.         otg.bulkout_max_pktsize = FS_BULK_PKT_SIZE;
  1757.     }
  1758. }

  1760. void s3c_usb_set_endpoint(void)
  1761. {
  1762.     /* Unmask S5P_OTG_DAINT source */
  1763.     writel(0xff, S5P_OTG_DIEPINT0);
  1764.     writel(0xff, S5P_OTG_DOEPINT0);
  1765.     writel(0xff, S5P_OTG_DIEPINT_IN);
  1766.     writel(0xff, S5P_OTG_DOEPINT_OUT);

  1768.     /* Init For Ep0*/
  1769.     if(otg.speed == USB_HIGH)
  1770.     {
  1771.         /*MPS:64bytes */
  1772.         writel(((1<<26)|(CONTROL_EP<<11)|(0<<0)), S5P_OTG_DIEPCTL0);
  1773.         /*ep0 enable, clear nak */
  1774.         writel((1u<<31)|(1<<26)|(0<<0), S5P_OTG_DOEPCTL0);
  1775.     }
  1776.     else
  1777.     {
  1778.         /*MPS:8bytes */
  1779.         writel(((1<<26)|(CONTROL_EP<<11)|(3<<0)), S5P_OTG_DIEPCTL0);
  1780.         /*ep0 enable, clear nak */
  1781.         writel((1u<<31)|(1<<26)|(3<<0), S5P_OTG_DOEPCTL0);
  1782.     }
  1783. }

  1785. void s3c_usb_set_descriptors(void)
  1786. {
  1787.     /* Standard device descriptor */
  1788.     otg.desc.dev.bLength=DEVICE_DESC_SIZE;    /*0x12*/
  1789.     otg.desc.dev.bDescriptorType=DEVICE_DESCRIPTOR;
  1790.     otg.desc.dev.bDeviceClass=0xFF; /* 0x0*/
  1791.     otg.desc.dev.bDeviceSubClass=0x0;
  1792.     otg.desc.dev.bDeviceProtocol=0x0;
  1793.     otg.desc.dev.bMaxPacketSize0=otg.ctrl_max_pktsize;
  1794.     otg.desc.dev.idVendorL=0xE8;    /*0x45;*/
  1795.     otg.desc.dev.idVendorH=0x04;    /*0x53;*/
  1796.     otg.desc.dev.idProductL=0x34; /*0x00*/
  1797.     otg.desc.dev.idProductH=0x12; /*0x64*/
  1798.     otg.desc.dev.bcdDeviceL=0x00;
  1799.     otg.desc.dev.bcdDeviceH=0x01;
  1800.     otg.desc.dev.iManufacturer=0x1; /* index of string descriptor */
  1801.     otg.desc.dev.iProduct=0x2;    /* index of string descriptor */
  1802.     otg.desc.dev.iSerialNumber=0x0;
  1803.     otg.desc.dev.bNumConfigurations=0x1;
  1804.     if (otg.speed == USB_FULL) {
  1805.         otg.desc.dev.bcdUSBL=0x10;
  1806.         otg.desc.dev.bcdUSBH=0x01;    /* Ver 1.10*/
  1807.     }
  1808.     else {
  1809.         otg.desc.dev.bcdUSBL=0x00;
  1810.         otg.desc.dev.bcdUSBH=0x02;    /* Ver 2.0*/
  1811.     }

  1813.     /* Standard configuration descriptor */
  1814.     otg.desc.config.bLength=CONFIG_DESC_SIZE; /* 0x9 bytes */
  1815.     otg.desc.config.bDescriptorType=CONFIGURATION_DESCRIPTOR;
  1816.     otg.desc.config.wTotalLengthL=CONFIG_DESC_TOTAL_SIZE;
  1817.     otg.desc.config.wTotalLengthH=0;
  1818.     otg.desc.config.bNumInterfaces=1;
  1819. /* dbg     descConf.bConfigurationValue=2; // why 2? There's no reason.*/
  1820.     otg.desc.config.bConfigurationValue=1;
  1821.     otg.desc.config.iConfiguration=0;
  1822.     otg.desc.config.bmAttributes=CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED; /* bus powered only.*/
  1823.     otg.desc.config.maxPower=25; /* draws 50mA current from the USB bus.*/

  1825.     /* Standard interface descriptor */
  1826.     otg.desc.intf.bLength=INTERFACE_DESC_SIZE; /* 9*/
  1827.     otg.desc.intf.bDescriptorType=INTERFACE_DESCRIPTOR;
  1828.     otg.desc.intf.bInterfaceNumber=0x0;
  1829.     otg.desc.intf.bAlternateSetting=0x0; /* ?*/
  1830.     otg.desc.intf.bNumEndpoints = 2;    /* # of endpoints except EP0*/
  1831.     otg.desc.intf.bInterfaceClass=0xff; /* 0x0 ?*/
  1832.     otg.desc.intf.bInterfaceSubClass=0x0;
  1833.     otg.desc.intf.bInterfaceProtocol=0x0;
  1834.     otg.desc.intf.iInterface=0x0;

  1836.     /* Standard endpoint0 descriptor */
  1837.     otg.desc.ep1.bLength=ENDPOINT_DESC_SIZE;
  1838.     otg.desc.ep1.bDescriptorType=ENDPOINT_DESCRIPTOR;
  1839.     otg.desc.ep1.bEndpointAddress=BULK_IN_EP|EP_ADDR_IN;
  1840.     otg.desc.ep1.bmAttributes=EP_ATTR_BULK;
  1841.     otg.desc.ep1.wMaxPacketSizeL=(u8)otg.bulkin_max_pktsize; /* 64*/
  1842.     otg.desc.ep1.wMaxPacketSizeH=(u8)(otg.bulkin_max_pktsize>>8);
  1843.     otg.desc.ep1.bInterval=0x0; /* not used */

  1845.     /* Standard endpoint1 descriptor */
  1846.     otg.desc.ep2.bLength=ENDPOINT_DESC_SIZE;
  1847.     otg.desc.ep2.bDescriptorType=ENDPOINT_DESCRIPTOR;
  1848.     otg.desc.ep2.bEndpointAddress=BULK_OUT_EP|EP_ADDR_OUT;
  1849.     otg.desc.ep2.bmAttributes=EP_ATTR_BULK;
  1850.     otg.desc.ep2.wMaxPacketSizeL=(u8)otg.bulkout_max_pktsize; /* 64*/
  1851.     otg.desc.ep2.wMaxPacketSizeH=(u8)(otg.bulkout_max_pktsize>>8);
  1852.     otg.desc.ep2.bInterval=0x0; /* not used */
  1853. }

  1855. void s3c_usb_check_speed(USB_SPEED *speed)
  1856. {
  1857.     u32 status;

  1859.     status = readl(S5P_OTG_DSTS); /* System status read */

  1861.     *speed = (USB_SPEED)((status&0x6) >>1);
  1862. }

  1864. void s3c_usb_clear_dnfile_info(void)
  1865. {
  1866.     otg.dn_addr = 0;
  1867.     otg.dn_filesize = 0;
  1868.     otg.dn_ptr = 0;
  1869. }

  1871. void s3c_usb_clear_upfile_info(void)
  1872. {
  1873.     otg.up_addr= 0;
  1874.     otg.up_size= 0;
  1875.     otg.up_ptr = 0;
  1876. }


  1879. int s3c_usb_check_setconf(void)
  1880. {
  1881.     if (otg.set_config == 0)
  1882.         return FALSE;
  1883.     else
  1884.         return TRUE;
  1885. }

  1887. void s3c_usb_set_opmode(USB_OPMODE mode)
  1888. {
  1889.     otg.op_mode = mode;

  1891.     writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  1892.         INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY,
  1893.         S5P_OTG_GINTMSK); /*gint unmask */

  1895.     writel(MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK, S5P_OTG_GAHBCFG);

  1897.     s3c_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);
  1898.     s3c_usb_set_inep_xfersize(EP_TYPE_BULK, 1, 0);

  1900.     /*bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt */
  1901.     writel(1u<<31|1<<26|2<<18|1<<15|otg.bulkout_max_pktsize<<0,
  1902.         S5P_OTG_DOEPCTL_OUT);

  1904.     /*bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt */
  1905.     writel(0u<<31|1<<26|2<<18|1<<15|otg.bulkin_max_pktsize<<0,
  1906.         S5P_OTG_DIEPCTL_IN);
  1907. }

  1909. void s3c_usb_reset(void)
  1910. {
  1911.     s3c_usb_set_all_outep_nak();

  1913.     otg.ep0_state = EP0_STATE_INIT;
  1914.     writel(((1<<BULK_OUT_EP)|(1<<CONTROL_EP))<<16|((1<<BULK_IN_EP)|(1<<CONTROL_EP)),
  1915.         S5P_OTG_DAINTMSK);
  1916.     writel(CTRL_OUT_EP_SETUP_PHASE_DONE|AHB_ERROR|TRANSFER_DONE,
  1917.         S5P_OTG_DOEPMSK);
  1918.     writel(INTKN_TXFEMP|NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE,
  1919.         S5P_OTG_DIEPMSK);

  1921.     /* Rx FIFO Size */
  1922.     writel(RX_FIFO_SIZE, S5P_OTG_GRXFSIZ);

  1924.     /* Non Periodic Tx FIFO Size */
  1925.     writel(NPTX_FIFO_SIZE<<16| NPTX_FIFO_START_ADDR<<0, S5P_OTG_GNPTXFSIZ);

  1927.     s3c_usb_clear_all_outep_nak();

  1929.     /*clear device address */
  1930.     writel(readl(S5P_OTG_DCFG)&~(0x7f<<4), S5P_OTG_DCFG);

  1932.     if(SUSPEND_RESUME_ON) {
  1933.         writel(readl(S5P_OTG_PCGCCTL)&~(1<<0), S5P_OTG_PCGCCTL);
  1934.     }
  1935. }
  1936. int s3c_usb_set_init(void)
  1937. {
  1938.     u32 status;

  1940.     status = readl(S5P_OTG_DSTS); /* System status read */

  1942.     /* Set if Device is High speed or Full speed */
  1943.     if (((status&0x6) >>1) == USB_HIGH) {
  1944.         DBG_SETUP1("High Speed Detection\n");
  1945.         s3c_usb_set_max_pktsize(USB_HIGH);
  1946.     }
  1947.     else if(((status&0x6) >>1) == USB_FULL) {
  1948.         DBG_SETUP1("Full Speed Detec tion\n");
  1949.         s3c_usb_set_max_pktsize(USB_FULL);
  1950.     }
  1951.     else {
  1952.         printf("**** Error:Neither High_Speed nor Full_Speed\n");
  1953.         return FALSE;
  1954.     }

  1956.     s3c_usb_set_endpoint();
  1957.     s3c_usb_set_descriptors();
  1958.     s3c_usb_clear_dnfile_info();
  1959.     s3c_usb_set_opmode(op_mode);

  1961.     return TRUE;
  1962. }

  1964. void s3c_usb_pkt_receive(void)
  1965. {
  1966.     u32 rx_status;
  1967.     u32 fifo_cnt_byte;

  1969.     rx_status = readl(S5P_OTG_GRXSTSP);
  1970.     DBG_SETUP0("S5P_OTG_GRXSTSP = 0x%x\n", rx_status);

  1972.     if ((rx_status & (0xf<<17)) == SETUP_PKT_RECEIVED) {
  1973.         DBG_SETUP1("SETUP_PKT_RECEIVED\n");
  1974.         s3c_usb_ep0_int_hndlr();

  1976.     } else if ((rx_status & (0xf<<17)) == OUT_PKT_RECEIVED) {
  1977.         fifo_cnt_byte = (rx_status & 0x7ff0)>>4;
  1978.         DBG_SETUP1("OUT_PKT_RECEIVED\n");

  1980.         if((rx_status & BULK_OUT_EP)&&(fifo_cnt_byte)) {
  1981.             s3c_usb_int_bulkout(fifo_cnt_byte);
  1982.             if( otg.op_mode == USB_CPU )
  1983.                 writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|
  1984.                     INT_ENUMDONE|INT_RESET|INT_SUSPEND|
  1985.                     INT_RX_FIFO_NOT_EMPTY,
  1986.                     S5P_OTG_GINTMSK);
  1987.             return;
  1988.         }

  1990.     } else if ((rx_status & (0xf<<17)) == GLOBAL_OUT_NAK) {
  1991.         DBG_SETUP1("GLOBAL_OUT_NAK\n");

  1993.     } else if ((rx_status & (0xf<<17)) == OUT_TRNASFER_COMPLETED) {
  1994.         DBG_SETUP1("OUT_TRNASFER_COMPLETED\n");

  1996.     } else if ((rx_status & (0xf<<17)) == SETUP_TRANSACTION_COMPLETED) {
  1997.         DBG_SETUP1("SETUP_TRANSACTION_COMPLETED\n");

  1999.     } else {
  2000.         DBG_SETUP1("Reserved\n");
  2001.     }
  2002. }

  2004. void s3c_usb_transfer(void)
  2005. {
  2006.     u32 ep_int;
  2007.     u32 check_dma;
  2008.     u32 ep_int_status;

  2010.     ep_int = readl(S5P_OTG_DAINT);
  2011.     DBG_SETUP0("S5P_OTG_DAINT = 0x%x", ep_int);

  2013.     if (ep_int & (1<<CONTROL_EP)) {
  2014.         ep_int_status = readl(S5P_OTG_DIEPINT0);
  2015.         DBG_SETUP1("S5P_OTG_DIEPINT0 : %x \n", ep_int_status);

  2017.         if (ep_int_status & INTKN_TXFEMP) {
  2018.             u32 uNTxFifoSpace;
  2019.             do {
  2020.                 uNTxFifoSpace=readl(S5P_OTG_GNPTXSTS)&0xffff;
  2021.             }while(uNTxFifoSpace<otg.ctrl_max_pktsize);

  2023.             s3c_usb_transfer_ep0();
  2024.         }

  2026.         writel(ep_int_status, S5P_OTG_DIEPINT0); /* Interrupt Clear */
  2027.     }

  2029.     if (ep_int & ((1<<CONTROL_EP)<<16)) {
  2030.         ep_int_status = readl(S5P_OTG_DOEPINT0);
  2031.         DBG_SETUP1("S5P_OTG_DOEPINT0 : %x \n", ep_int_status);

  2033.         s3c_usb_set_outep_xfersize(EP_TYPE_CONTROL, 1, 8);
  2034.         writel(1u<<31|1<<26, S5P_OTG_DOEPCTL0); /*ep0 enable, clear nak */

  2036.         writel(ep_int_status, S5P_OTG_DOEPINT0); /* Interrupt Clear */
  2037.     }

  2039.     if(ep_int & (1<<BULK_IN_EP)) {
  2040.         ep_int_status = readl(S5P_OTG_DIEPINT_IN);
  2041.         DBG_BULK1("S5P_OTG_DIEPINT_IN : %x \n", ep_int_status);
  2042.         writel(ep_int_status, S5P_OTG_DIEPINT_IN); /* Interrupt Clear */

  2044.         if ( (ep_int_status&INTKN_TXFEMP) && otg.op_mode == USB_CPU)
  2045.             s3c_usb_int_bulkin();

  2047.         check_dma = readl(S5P_OTG_GAHBCFG);
  2048.         if ((check_dma&MODE_DMA)&&(ep_int_status&TRANSFER_DONE))
  2049.             s3c_usb_dma_in_done();
  2050.     }

  2052.     if (ep_int & ((1<<BULK_OUT_EP)<<16)) {
  2053.         ep_int_status = readl(S5P_OTG_DOEPINT_OUT);
  2054.         DBG_BULK1("S5P_OTG_DOEPINT_OUT : 0x%x\n", ep_int_status);
  2055.         writel(ep_int_status, S5P_OTG_DOEPINT_OUT); /* Interrupt Clear */

  2057.         check_dma = readl(S5P_OTG_GAHBCFG);
  2058.         if ((check_dma&MODE_DMA)&&(ep_int_status&TRANSFER_DONE)) {
  2059.             s3c_usb_dma_out_done();
  2060.         }
  2061.     }
  2062. }

  2064. void s3c_udc_int_hndlr(void)
  2065. {
  2066.     u32 int_status;
  2067.     int tmp;

  2069.     int_status = readl(S5P_OTG_GINTSTS); /* Core Interrupt Register */
  2070.     writel(int_status, S5P_OTG_GINTSTS); /* Interrupt Clear */
  2071.     DBG_SETUP0("*** USB OTG Interrupt(S5P_OTG_GINTSTS: 0x%08x) ****\n",
  2072.         int_status);

  2074.     if (int_status & INT_RESET) {
  2075.         DBG_SETUP1("INT_RESET\n");
  2076.         writel(INT_RESET, S5P_OTG_GINTSTS); /* Interrupt Clear */

  2078.         s3c_usb_reset();
  2079.     }

  2081.     if (int_status & INT_ENUMDONE) {
  2082.         DBG_SETUP1("INT_ENUMDONE :");
  2083.         writel(INT_ENUMDONE, S5P_OTG_GINTSTS); /* Interrupt Clear */
  2084.         s3c_usb_connected_status=3;
  2085.         tmp = s3c_usb_set_init();
  2086.         if (tmp == FALSE)
  2087.             return;

  2089.     }

  2091.     if (int_status & INT_RESUME) {
  2092.         DBG_SETUP1("INT_RESUME\n");
  2093.         writel(INT_RESUME, S5P_OTG_GINTSTS); /* Interrupt Clear */

  2095.         if(SUSPEND_RESUME_ON) {
  2096.             writel(readl(S5P_OTG_PCGCCTL)&~(1<<0), S5P_OTG_PCGCCTL);
  2097.             DBG_SETUP1("INT_RESUME\n");
  2098.         }
  2099.     }

  2101.     if (int_status & INT_SUSPEND) {
  2102.         DBG_SETUP1("INT_SUSPEND\n");
  2103.         writel(INT_SUSPEND, S5P_OTG_GINTSTS); /* Interrupt Clear */

  2105.         if(SUSPEND_RESUME_ON) {
  2106.             writel(readl(S5P_OTG_PCGCCTL)|(1<<0), S5P_OTG_PCGCCTL);
  2107.         }
  2108.     }

  2110.     if(int_status & INT_RX_FIFO_NOT_EMPTY) {
  2111.         DBG_SETUP1("INT_RX_FIFO_NOT_EMPTY\n");
  2112.         /* Read only register field */

  2114.         writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|
  2115.             INT_ENUMDONE|INT_RESET|INT_SUSPEND,
  2116.             S5P_OTG_GINTMSK);
  2117.         s3c_usb_pkt_receive();
  2118.         writel(INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|
  2119.             INT_RESET |INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY,
  2120.             S5P_OTG_GINTMSK); /*gint unmask */
  2121.         s3c_usb_connected_status=1;
  2122.     }

  2124.     if ((int_status & INT_IN_EP) || (int_status & INT_OUT_EP)) {
  2125.         DBG_SETUP1("INT_IN or OUT_EP\n");
  2126.         /* Read only register field */

  2128.         s3c_usb_transfer();
  2129.     }
  2130. }

  2132. int s3c_udc_is_adc_cable()
  2133. {
  2134.     int count = 0;
  2135.     while(count<10)
  2136.         {
  2137.     if((readl(S5P_OTG_HPRT)&0xc00)==0xc00)
  2138.         count ++;
  2139.     else
  2140.         {
  2141.             count =0;
  2142.             return 0;
  2143.         }
  2144.     }
  2145.     return 1;
  2146. }
  2147. /*the following is for u-boot battery charge*/
  2148. int s3c_check_usb_connect_status()
  2149. {
  2150.     if(!s3c_usb_phy_inited)/*initalized at first*/
  2151.     {    
  2152.         s3c_usbctl_init(1);
  2153.     }
  2154.     /*then check current usb status*/
  2155.     unsigned long usec = (1000*1000*10);
  2156.     ulong tmo, tmp;

  2158.     if (usec >= 1000) {        /* if "big" number, spread normalization to seconds */
  2159.         tmo = usec / 1000;    /* start to normalize for usec to ticks per sec */
  2160.         tmo *= CFG_HZ;        /* find number of "ticks" to wait to achieve target */
  2161.         tmo /= 1000;        /* finish normalize. */
  2162.     }
  2163.     else {                /* else small number, don't kill it prior to HZ multiply */
  2164.         tmo = usec * CFG_HZ;
  2165.         tmo /= (1000 * 1000);
  2166.     }
  2167.     tmp = get_timer(0);        /* get current timestamp */
  2168.     if ((tmo + tmp + 1) < tmp)    /* if setting this fordward will roll time stamp */
  2169.     {        
  2170.         reset_timer_masked();    /* reset "advancing" timestamp to 0, set lastdec value */
  2171.     }
  2172.     else
  2173.         tmo += tmp;        /* else, set advancing stamp wake up time */

  2175.     while (get_timer_masked()<tmo)    
  2176.     {
  2177.         if (S3C_USBD_DETECT_IRQ()) {
  2178.             s3c_udc_int_hndlr();
  2179.             S3C_USBD_CLEAR_IRQ();
  2180.         }
  2181.         if(s3c_udc_is_adc_cable())
  2182.             s3c_usb_connected_status=2;
  2183.         if(s3c_usb_connected_status==2||s3c_usb_connected_status==1)
  2184.             break;
  2185.     }
  2186.     
  2187.     if(s3c_usb_phy_inited)
  2188.     {        
  2189.         s3c_usb_stop();
  2190.     }
  2191.     return s3c_usb_connected_status;
  2192.     
  2193. }
  2194. #endif

usbd-otg-hs.h

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  1. /*
  2.  * cpu/s5pc1xx/usbd-otg-hs.h
  3.  *
  4.  * (C) Copyright 2009
  5.  * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
  6.  *    - only support for S5PC100
  7.  *
  8.  * This program is free software; you can redistribute it and/or
  9.  * modify it under the terms of the GNU General Public License as
  10.  * published by the Free Software Foundation; either version 2 of
  11.  * the License, or (at your option) any later version.
  12.  *
  13.  * This program is distributed in the hope that it will be useful,
  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16.  * GNU General Public License for more details.
  17.  *
  18.  * You should have received a copy of the GNU General Public License
  19.  * along with this program; if not, write to the Free Software
  20.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21.  * MA 02111-1307 USA
  22.  */

  24. #ifndef __S3C_OTG_HS_H__
  25. #define __S3C_OTG_HS_H__

  27. #include <asm/byteorder.h>
  28. #include <asm/arch/hardware.h>
  29. #include <asm/io.h>

  31. #define S3C_USBD_DETECT_IRQ()    (readl(S5P_OTG_GINTSTS) & \
  32.                     (GINTSTS_WkUpInt|GINTSTS_OEPInt|GINTSTS_IEPInt| \
  33.                      GINTSTS_EnumDone|GINTSTS_USBRst|GINTSTS_USBSusp|GINTSTS_RXFLvl))
  34. #define S3C_USBD_CLEAR_IRQ()    do { \
  35.                     writel(BIT_ALLMSK, (S5P_OTG_GINTSTS)); \
  36.                 } while (0)

  38. #define CONTROL_EP        0
  39. #define BULK_IN_EP        1
  40. #define BULK_OUT_EP        2

  42. #define FS_CTRL_PKT_SIZE    8
  43. #define FS_BULK_PKT_SIZE    64

  45. #define HS_CTRL_PKT_SIZE    64
  46. #define HS_BULK_PKT_SIZE    512

  48. #define RX_FIFO_SIZE        512
  49. #define NPTX_FIFO_START_ADDR    RX_FIFO_SIZE
  50. #define NPTX_FIFO_SIZE        512
  51. #define PTX_FIFO_SIZE        512

  53. // string descriptor
  54. #define LANGID_US_L        (0x09)
  55. #define LANGID_US_H        (0x04)

  57. // Feature Selectors
  58. #define EP_STALL        0
  59. #define DEVICE_REMOTE_WAKEUP    1
  60. #define TEST_MODE        2

  62. /* Test Mode Selector*/
  63. #define TEST_J            1
  64. #define TEST_K            2
  65. #define TEST_SE0_NAK        3
  66. #define TEST_PACKET        4
  67. #define TEST_FORCE_ENABLE    5

  69. #define S5P_OTG_DIEPCTL_IN    (S5P_OTG_DIEPCTL0 + 0x20*BULK_IN_EP)
  70. #define S5P_OTG_DIEPINT_IN    (S5P_OTG_DIEPINT0 + 0x20*BULK_IN_EP)
  71. #define S5P_OTG_DIEPTSIZ_IN    (S5P_OTG_DIEPTSIZ0 + 0x20*BULK_IN_EP)
  72. #define S5P_OTG_DIEPDMA_IN    (S5P_OTG_DIEPDMA0 + 0x20*BULK_IN_EP)
  73. #define S5P_OTG_DOEPCTL_OUT    (S5P_OTG_DOEPCTL0 + 0x20*BULK_OUT_EP)
  74. #define S5P_OTG_DOEPINT_OUT    (S5P_OTG_DOEPINT0 + 0x20*BULK_OUT_EP)
  75. #define S5P_OTG_DOEPTSIZ_OUT    (S5P_OTG_DOEPTSIZ0 + 0x20*BULK_OUT_EP)
  76. #define S5P_OTG_DOEPDMA_OUT    (S5P_OTG_DOEPDMA0 + 0x20*BULK_OUT_EP)
  77. #define S5P_OTG_IN_FIFO        (S5P_OTG_EP0_FIFO + 0x1000*BULK_IN_EP)
  78. #define S5P_OTG_OUT_FIFO    (S5P_OTG_EP0_FIFO + 0x1000*BULK_OUT_EP)


  81. typedef struct
  82. {
  83.     u8 bLength;
  84.     u8 bDescriptorType;
  85.     u8 bcdUSBL;
  86.     u8 bcdUSBH;
  87.     u8 bDeviceClass;
  88.     u8 bDeviceSubClass;
  89.     u8 bDeviceProtocol;
  90.     u8 bMaxPacketSize0;
  91.     u8 idVendorL;
  92.     u8 idVendorH;
  93.     u8 idProductL;
  94.     u8 idProductH;
  95.     u8 bcdDeviceL;
  96.     u8 bcdDeviceH;
  97.     u8 iManufacturer;
  98.     u8 iProduct;
  99.     u8 iSerialNumber;
  100.     u8 bNumConfigurations;
  101. } __attribute__ ((packed)) device_desc_t;

  103. typedef struct
  104. {
  105.     u8 bLength;
  106.     u8 bDescriptorType;
  107.     u8 wTotalLengthL;
  108.     u8 wTotalLengthH;
  109.     u8 bNumInterfaces;
  110.     u8 bConfigurationValue;
  111.     u8 iConfiguration;
  112.     u8 bmAttributes;
  113.     u8 maxPower;
  114. } __attribute__ ((packed)) config_desc_t;

  116. typedef struct
  117. {
  118.     u8 bLength;
  119.     u8 bDescriptorType;
  120.     u8 bInterfaceNumber;
  121.     u8 bAlternateSetting;
  122.     u8 bNumEndpoints;
  123.     u8 bInterfaceClass;
  124.     u8 bInterfaceSubClass;
  125.     u8 bInterfaceProtocol;
  126.     u8 iInterface;
  127. } __attribute__ ((packed)) intf_desc_t;

  129. typedef struct
  130. {
  131.     u8 bLength;
  132.     u8 bDescriptorType;
  133.     u8 bEndpointAddress;
  134.     u8 bmAttributes;
  135.     u8 wMaxPacketSizeL;
  136.     u8 wMaxPacketSizeH;
  137.     u8 bInterval;
  138. } __attribute__ ((packed)) ep_desc_t;

  140. typedef struct
  141. {
  142.     u8 bmRequestType;
  143.     u8 bRequest;
  144.     u8 wValue_L;
  145.     u8 wValue_H;
  146.     u8 wIndex_L;
  147.     u8 wIndex_H;
  148.     u8 wLength_L;
  149.     u8 wLength_H;
  150. } __attribute__ ((packed)) device_req_t;

  152. typedef struct
  153. {
  154.     device_desc_t dev;
  155.     config_desc_t config;
  156.     intf_desc_t intf;
  157.     ep_desc_t ep1;
  158.     ep_desc_t ep2;
  159.     ep_desc_t ep3;
  160.     ep_desc_t ep4;
  161. } __attribute__ ((packed)) descriptors_t;

  163. typedef struct
  164. {
  165.     u8 Device;
  166.     u8 Interface;
  167.     u8 ep_ctrl;
  168.     u8 ep_in;
  169.     u8 ep_out;
  170. } __attribute__ ((packed)) get_status_t;

  172. typedef struct
  173. {
  174.     u8 AlternateSetting;
  175. } __attribute__ ((packed)) get_intf_t;


  178. typedef enum
  179. {
  180.     USB_CPU, USB_DMA
  181. } USB_OPMODE;

  183. typedef enum
  184. {
  185.     USB_HIGH, USB_FULL, USB_LOW
  186. } USB_SPEED;

  188. typedef enum
  189. {
  190.     EP_TYPE_CONTROL, EP_TYPE_ISOCHRONOUS, EP_TYPE_BULK, EP_TYPE_INTERRUPT
  191. } EP_TYPE;


  194. typedef struct
  195. {
  196.     descriptors_t desc;
  197.     device_req_t dev_req;

  199.     u32 ep0_state;
  200.     u32 ep0_substate;
  201.     USB_OPMODE op_mode;
  202.     USB_SPEED speed;
  203.     u32 ctrl_max_pktsize;
  204.     u32 bulkin_max_pktsize;
  205.     u32 bulkout_max_pktsize;
  206.     u32 dn_addr;
  207.     u32 dn_filesize;
  208.     u32 up_addr;
  209.     u32 up_size;
  210.     u8* dn_ptr;
  211.     u8* up_ptr;
  212.     u32 set_config;
  213.     u32 req_length;
  214. } __attribute__ ((packed)) otg_dev_t;

  216. // SPEC1.1

  218. // Standard bmRequestType (direction)
  219. enum DEV_REQUEST_DIRECTION
  220. {
  221.     HOST_TO_DEVICE                = 0x00,
  222.     DEVICE_TO_HOST                = 0x80
  223. };

  225. // Standard bmRequestType (Type)
  226. enum DEV_REQUEST_TYPE
  227. {
  228.     STANDARD_TYPE            = 0x00,
  229.     CLASS_TYPE            = 0x20,
  230.     VENDOR_TYPE            = 0x40,
  231.     RESERVED_TYPE            = 0x60
  232. };

  234. // Standard bmRequestType (Recipient)
  235. enum DEV_REQUEST_RECIPIENT
  236. {
  237.     DEVICE_RECIPIENT        = 0,
  238.     INTERFACE_RECIPIENT        = 1,
  239.     ENDPOINT_RECIPIENT        = 2,
  240.     OTHER_RECIPIENT            = 3
  241. };

  243. // Descriptor types
  244. enum DESCRIPTOR_TYPE
  245. {
  246.     DEVICE_DESCRIPTOR        = 1,
  247.     CONFIGURATION_DESCRIPTOR    = 2,
  248.     STRING_DESCRIPTOR        = 3,
  249.     INTERFACE_DESCRIPTOR        = 4,
  250.     ENDPOINT_DESCRIPTOR        = 5,
  251.     DEVICE_QUALIFIER        = 6,
  252.     OTHER_SPEED_CONFIGURATION    = 7,
  253.     INTERFACE_POWER            = 8
  254. };

  256. // configuration descriptor: bmAttributes
  257. enum CONFIG_ATTRIBUTES
  258. {
  259.     CONF_ATTR_DEFAULT        = 0x80,
  260.     CONF_ATTR_REMOTE_WAKEUP     = 0x20,
  261.     CONF_ATTR_SELFPOWERED        = 0x40
  262. };

  264. // endpoint descriptor
  265. enum ENDPOINT_ATTRIBUTES
  266. {
  267.     EP_ADDR_IN            = 0x80,
  268.     EP_ADDR_OUT            = 0x00,

  270.     EP_ATTR_CONTROL            = 0x0,
  271.     EP_ATTR_ISOCHRONOUS        = 0x1,
  272.     EP_ATTR_BULK            = 0x2,
  273.     EP_ATTR_INTERRUPT        = 0x3
  274. };

  276. // Standard bRequest codes
  277. enum STANDARD_REQUEST_CODE
  278. {
  279.     STANDARD_GET_STATUS        = 0,
  280.     STANDARD_CLEAR_FEATURE        = 1,
  281.     STANDARD_RESERVED_1        = 2,
  282.     STANDARD_SET_FEATURE        = 3,
  283.     STANDARD_RESERVED_2        = 4,
  284.     STANDARD_SET_ADDRESS        = 5,
  285.     STANDARD_GET_DESCRIPTOR        = 6,
  286.     STANDARD_SET_DESCRIPTOR        = 7,
  287.     STANDARD_GET_CONFIGURATION    = 8,
  288.     STANDARD_SET_CONFIGURATION    = 9,
  289.     STANDARD_GET_INTERFACE        = 10,
  290.     STANDARD_SET_INTERFACE        = 11,
  291.     STANDARD_SYNCH_FRAME        = 12
  292. };

  294. int s3c_usbctl_init(int ischeckstatus);
  295. int s3c_usbc_activate (void);
  296. int s3c_usb_stop( void );
  297. void s3c_udc_int_hndlr(void);

  299. /* in usbd-otg-hs.c */
  300. extern unsigned int s3c_usbd_dn_addr;
  301. extern unsigned int s3c_usbd_dn_cnt;
  302. extern int DNW;
  303. extern int s3c_got_header;
  304. extern int s3c_receive_done;

  306. #endif



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