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分类: 嵌入式

2016-01-06 10:24:05

先看看K9F4G的重要时序:






对于三星的cpu,只需要设置3个参数:
tALS:  ALE Setup time = 12ns
tWP: WE Pulse Width = 12
tCLH / tALH: Hold Time = 5ns

补充一下,K9F4G属于异步nand,以前一直搞不清楚到底什么是异步芯片,什么的同步芯片,虽然当初搞fpga的时候有同步和异步的概念,但是到具体芯片上却分不清楚,现在弄明白了,像K9F4G这种,没有clk信号引脚,而是靠CE WE RE进行读写控制的,100%是异步芯片,而那些有CLK的,则是同步芯片。

而AM335x的参数就比较多了:
GPMC有CONFIG1 ~CONIG7共7个寄存器
CONFIG1,对于异步nand,设置[11-10] = 0x2h, 其他位设为0就好了。,即0x00000800。

EVM采用MT29F2G08这颗芯片,256MB(2Gbits),看看u-boot默认值:
#define M_NAND_GPMC_CONFIG1    0x00000800         /* MUXADDDATA = 0*/

#define M_NAND_GPMC_CONFIG2    0x001e1e00                                    /*CSWROFFTIME = CSRDOFFTIME = 0x1e  = 30clk*/

#define M_NAND_GPMC_CONFIG3    0x001e1e00                                    /* ADVWROFFTIME ADVRDOFFTIME = 30clk */

#define M_NAND_GPMC_CONFIG4    0x16051807                                  
  /*  [28-24]WEOFFTIME = 22 clk,  WEONTIME = 5 clk  ,  /* OEAADMUXOFFTIME = 24 clk, OEONTIME= 7clk */

#define M_NAND_GPMC_CONFIG5    0x00151e1e                                    /*RDACCESSTIME=0x15, WRCYCLETIME=RDCYCLETIME = 0x1e*/

#define M_NAND_GPMC_CONFIG6    0x16000f80                                   
/*WRACCESSTIME=0x16,*/ /*CYCLE2CYCLEDELAY=0xf,CYCLE2CYCLESAMECS=0x8*/

#define M_NAND_GPMC_CONFIG7    0x00000008                                    /*[5:0]BASEADDRESS=0x8,*/
/*CSi base address where i = 0 to 3 (16 Mbytes minimum granularity).*/
Bits 5 to 0 correspond to A29, A28, A27, A26, A25, and A24*/


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  1. /* GMPC clk = Core Clock M4 / 2= 100MHZ, tclk = 10ns */

  2. #define M_NAND_GPMC_CONFIG1 0x00000800    /* MUXADDDATA = 0 */

  3. #define M_NAND_GPMC_CONFIG2 0x001e1e00    /*CSWROFFTIME = CSRDOFFTIME = 0x1e = 30clk*/

  4. #define M_NAND_GPMC_CONFIG3 0x001e1e00    /* ADVWROFFTIME ADVRDOFFTIME = 30clk */

  5. #define M_NAND_GPMC_CONFIG4 0x16051807    /* [28-24]WEOFFTIME = 22 clk, WEONTIME = 5 clk , OEAADMUXOFFTIME = 24 clk, OEONTIME= 7clk */

  6. #define M_NAND_GPMC_CONFIG5 0x00151e1e    /*RDACCESSTIME=0x15, WRCYCLETIME=RDCYCLETIME = 0x1e*/

  7. #define M_NAND_GPMC_CONFIG6 0x16000f80    /*WRACCESSTIME=0x16,*/ /*CYCLE2CYCLEDELAY=0xf= 15 clk,CYCLE2CYCLESAMECS=0x8*/

  8. #define M_NAND_GPMC_CONFIG7 0x00000008     /*[5:0]BASEADDRESS=0x8,*/
  9. /*CSi base address where i = 0 to 3 (16 Mbytes minimum granularity).Bits 5 to 0 correspond to A29, A28, A27, A26, A25, and A24*/

GMPC clk = Core Clock M4 / 2= 100MHZ, tclk = 10ns
可以用宏定义时序:
#define _CSROFF     4         /* 44ns */    
#define _CSWOFF     4         /* 44ns */
#define _ADON       0         /* 6ns */
#define _ADROFF     4         /* 34ns */
#define _ADWOFF     4         /* 44ns */
#define _OEON       1         /* 0ns */
#define _OEOFF      3         /* 54ns */
#define _WEON       1         /* 0ns */
#define _WEOFF      3         /* 40ns */
#define _RDCY       4         /* 82ns */
#define _WRCY       4         /* 82ns */
#define _RDACC      4         /* 64ns */
#define _CSHIGH     6         /* 0ns */     /* 100ns tADL! 60ns tWHR! */
#define _WBURST     0         /* 0ns */
#define _WRACC      4         /* 40ns */
#define _BTURN      9         /* 100ns */     /* 100ns tRHW */
然后包含#include "asm/arch-omap3/omap3-regs.h" 这个头文件,就可以方便的设置时序了。

S34ML08G1的时序:

tCLS =
可见S34和三星的K9F4G的时序是基本相同的:
tALS:  ALE Setup time = 12ns
tWP: WE Pulse Width = 12
tCLH / tALH: 命令Hold Time = 5ns
接下来看看AM335 GPMC时序对应nand的哪些参数:


修改后的参数:
#define M_NAND_GPMC_CONFIG1 0x00000800    /*[11-10]DEVICETYPE =0x2=NAND, [9-8]MUXADDDATA = 0*/
    
#define M_NAND_GPMC_CONFIG2 0x00030300    /* [20-16]CSWROFFTIME = CSRDOFFTIME = tCS+tCH = 25ns, set 3clk = 30ns*/
    
#define M_NAND_GPMC_CONFIG3 0x00030300    /* ADVWROFFTIME ADVRDOFFTIME =(WEOFFTIME)= tCLS+tCLH = 12+5= 17ns, we set it to 30ns */
    
#define M_NAND_GPMC_CONFIG4 0x02000000    /* [28-24]WEOFFTIME = tWP = 12ns, WEONTIME = 0 , OEAADMUXOFFTIME = 0 clk, OEONTIME= 0 */
    
#define M_NAND_GPMC_CONFIG5 0x00020404    /* [20-16]RDACCESSTIME=tRP = 12ns , WRCYCLETIME=RDCYCLETIME = 25ns */
    
#define M_NAND_GPMC_CONFIG6 0x02000000    /* [28-24]WRACCESSTIME=tWP = 12ns,*/ /*CYCLE2CYCLEDELAY= 0 clk,CYCLE2CYCLESAMECS= 0*/
    
#define M_NAND_GPMC_CONFIG7 0x00000040     /*[6]CSVAILD = 1, [5:0]BASEADDRESS=0x0,*/
    /*CSi base address where i = 0 to 3 (16 Mbytes minimum granularity).Bits 5 to 0 correspond to A29, A28, A27, A26, A25, and A24*/




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