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S5PV210 DDR配置笔记

分类：嵌入式

2015-09-27 16:50:19

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/*
* dmc0 initialization at single type
*/
ldr r0, =0xf0000000
ldr r1, =0x00101000 /* phycontrol0 dll parameter setting */
str r1, [r0, #0x18]
ldr r1, =0x00000086 /* phycontrol1 dll parameter setting */
str r1, [r0, #0x1c]
ldr r1, =0x00101002 /* phycontrol0 dll on */
str r1, [r0, #0x18]
ldr r1, =0x00101003 /* phycontrol0 dll start */
str r1, [r0, #0x18]
dmc0_lock:
ldr r1, [r0, #0x40] /* load phystatus register value */
and r2, r1, #0x7
cmp r2, #0x7 /* loop until dll is locked */
bne dmc0_lock
and r1, #0x3fc0
mov r2, r1, LSL #18
orr r2, r2, #0x100000
orr r2 ,r2, #0x1000
orr r1, r2, #0x3 /* force value locking */
str r1, [r0, #0x18]
/* setting ddr2 */
ldr r1, =0x0FFF2010 /* concontrol auto refresh off */
str r1, [r0, #0x00]
ldr r1, =0x00212400 /* memcontrol bl=4, 2 chip, ddr2 type, dynamic self refresh, force precharge, dynamic power down off */
str r1, [r0, #0x04]
ldr r1, =DMC0_MEMCONFIG_0 /* memconfig0 256MB config, 8 banks, mapping method[12:15] 0:linear, 1:linterleaved, 2:mixed */
str r1, [r0, #0x08]
ldr r1, =DMC0_MEMCONFIG_1 /* memconfig1 */
str r1, [r0, #0x0c]
ldr r1, =0xFF000000 /* prech config */
str r1, [r0, #0x14]
ldr r1, =DMC0_TIMINGA_REF /* timing aref */
str r1, [r0, #0x30]
ldr r1, =DMC0_TIMING_ROW /* timingRow */
str r1, [r0, #0x34]
ldr r1, =DMC0_TIMING_DATA /* timing data CL=3 */
str r1, [r0, #0x38]
ldr r1, =DMC0_TIMING_PWR /* timing power */
str r1, [r0, #0x3c]
ldr r1, =0x07000000 /* chip0 deselect */
str r1, [r0, #0x10]
ldr r1, =0x01000000 /* chip0 pall */
str r1, [r0, #0x10]
ldr r1, =0x00020000 /* chip0 emrs2 */
str r1, [r0, #0x10]
ldr r1, =0x00030000 /* chip0 emrs3 */
str r1, [r0, #0x10]
ldr r1, =0x00010400 /* chip0 emrs1 (mem dll on, dqs disable) */
str r1, [r0, #0x10]
ldr r1, =0x00000542 /* chip0 mrs (mem dll reset) cl=4, bl=4 */
str r1, [r0, #0x10]
ldr r1, =0x01000000 /* chip0 pall */
str r1, [r0, #0x10]
ldr r1, =0x05000000 /* chip0 refa */
str r1, [r0, #0x10]
ldr r1, =0x05000000 /* chip0 refa */
str r1, [r0, #0x10]
ldr r1, =0x00000442 /* chip0 mrs (mem dll unreset) */
str r1, [r0, #0x10]
ldr r1, =0x00010780 /* chip0 emrs1 (ocd default) */
str r1, [r0, #0x10]
ldr r1, =0x00010400 /* chip0 emrs1 (ocd exit) */
str r1, [r0, #0x10]
ldr r1, =0x07100000 /* chip1 deselect */
str r1, [r0, #0x10]
ldr r1, =0x01100000 /* chip1 pall */
str r1, [r0, #0x10]
ldr r1, =0x00120000 /* chip1 emrs2 */
str r1, [r0, #0x10]
ldr r1, =0x00130000 /* chip1 emrs3 */
str r1, [r0, #0x10]
ldr r1, =0x00110400 /* chip1 emrs1 (mem dll on, dqs disable) */
str r1, [r0, #0x10]
ldr r1, =0x00100542 /* chip1 mrs (mem dll reset) cl=4, bl=4 */
str r1, [r0, #0x10]
ldr r1, =0x01100000 /* chip1 pall */
str r1, [r0, #0x10]
ldr r1, =0x05100000 /* chip1 refa */
str r1, [r0, #0x10]
ldr r1, =0x05100000 /* chip1 refa */
str r1, [r0, #0x10]
ldr r1, =0x00100442 /* chip1 mrs (mem dll unreset) */
str r1, [r0, #0x10]
ldr r1, =0x00110780 /* chip1 emrs1 (ocd default) */
str r1, [r0, #0x10]
ldr r1, =0x00110400 /* chip1 emrs1 (ocd exit) */
str r1, [r0, #0x10]
ldr r1, =0x0FF02030 /* concontrol auto refresh on */
str r1, [r0, #0x00]
ldr r1, =0xFFFF00FF /* pwrdn config */
str r1, [r0, #0x28]
ldr r1, =0x00202400 /* memcontrol bl=4, 2 chip, ddr2 type, dynamic self refresh, force precharge, dynamic power down off */
str r1, [r0, #0x04]
/*
* dmc1 initialization at single type
*/
ldr r0, =0xf1400000
ldr r1, =0x00101000 /* phycontrol0 dll parameter setting */
str r1, [r0, #0x18]
ldr r1, =0x00000086 /* phycontrol1 dll parameter setting */
str r1, [r0, #0x1c]
ldr r1, =0x00101002 /* phycontrol0 dll on */
str r1, [r0, #0x18]
ldr r1, =0x00101003 /* phycontrol0 dll start */
str r1, [r0, #0x18]
dmc1_lock:
ldr r1, [r0, #0x40] /* load phystatus register value */
and r2, r1, #0x7
cmp r2, #0x7 /* loop until dll is locked */
bne dmc1_lock
and r1, #0x3fc0
mov r2, r1, LSL #18
orr r2, r2, #0x100000
orr r2 ,r2, #0x1000
orr r1, r2, #0x3 /* force value locking */
str r1, [r0, #0x18]
/* setting ddr2 */
ldr r1, =0x0FFF2010 /* concontrol auto refresh off */
str r1, [r0, #0x00]
ldr r1, =0x00212400 /* memcontrol bl=(2)4, (1)2 chip, (2)32bit, ddr2 type=(4)DDR2, dynamic self refresh, force precharge, dynamic power down off */
str r1, [r0, #0x04] /*[22:20]=2,[19:16]=1(2 chip),*/
ldr r1, =DMC1_MEMCONFIG_0 /* memconfig0 256MB config, 8 banks, mapping method[12:15] 0:linear, 1:linterleaved, 2:mixed */
str r1, [r0, #0x08]
ldr r1, =DMC1_MEMCONFIG_1 /* memconfig1 */
str r1, [r0, #0x0c]
ldr r1, =0xFF000000 /* prech config */
str r1, [r0, #0x14]
ldr r1, =DMC1_TIMINGA_REF /* timing aref */
str r1, [r0, #0x30]
ldr r1, =DMC1_TIMING_ROW /* timingRow */
str r1, [r0, #0x34]
ldr r1, =DMC1_TIMING_DATA /* timing data CL=3 */
str r1, [r0, #0x38]
ldr r1, =DMC1_TIMING_PWR /* timing power */
str r1, [r0, #0x3c]
ldr r1, =0x07000000 /* chip0 deselect */
str r1, [r0, #0x10]
ldr r1, =0x01000000 /* chip0 pall */
str r1, [r0, #0x10]
ldr r1, =0x00020000 /* chip0 emrs2 */
str r1, [r0, #0x10]
ldr r1, =0x00030000 /* chip0 emrs3 */
str r1, [r0, #0x10]
ldr r1, =0x00010400 /* chip0 emrs1 (mem dll on, dqs disable) */
str r1, [r0, #0x10]
ldr r1, =0x00000542 /* chip0 mrs (mem dll reset) cl=4, bl=4 */
str r1, [r0, #0x10]
ldr r1, =0x01000000 /* chip0 pall */
str r1, [r0, #0x10]
ldr r1, =0x05000000 /* chip0 refa */
str r1, [r0, #0x10]
ldr r1, =0x05000000 /* chip0 refa */
str r1, [r0, #0x10]
ldr r1, =0x00000442 /* chip0 mrs (mem dll unreset) */
str r1, [r0, #0x10]
ldr r1, =0x00010780 /* chip0 emrs1 (ocd default) */
str r1, [r0, #0x10]
ldr r1, =0x00010400 /* chip0 emrs1 (ocd exit) */
str r1, [r0, #0x10]
ldr r1, =0x07100000 /* chip1 deselect */
str r1, [r0, #0x10]
ldr r1, =0x01100000 /* chip1 pall */
str r1, [r0, #0x10]
ldr r1, =0x00120000 /* chip1 emrs2 */
str r1, [r0, #0x10]
ldr r1, =0x00130000 /* chip1 emrs3 */
str r1, [r0, #0x10]
ldr r1, =0x00110400 /* chip1 emrs1 (mem dll on, dqs disable) */
str r1, [r0, #0x10]
ldr r1, =0x00100542 /* chip1 mrs (mem dll reset) cl=4, bl=4 */
str r1, [r0, #0x10]
ldr r1, =0x01100000 /* chip1 pall */
str r1, [r0, #0x10]
ldr r1, =0x05100000 /* chip1 refa */
str r1, [r0, #0x10]
ldr r1, =0x05100000 /* chip1 refa */
str r1, [r0, #0x10]
ldr r1, =0x00100442 /* chip1 mrs (mem dll unreset) */
str r1, [r0, #0x10]
ldr r1, =0x00110780 /* chip1 emrs1 (ocd default) */
str r1, [r0, #0x10]
ldr r1, =0x00110400 /* chip1 emrs1 (ocd exit) */
str r1, [r0, #0x10]
ldr r1, =0x0FF02030 /* concontrol auto refresh on */
str r1, [r0, #0x00]
ldr r1, =0xFFFF00FF /* pwrdn config */
str r1, [r0, #0x28]
ldr r1, =0x00202400 /* memcontrol bl=4, 1 chip, ddr2 type, dynamic self refresh, force precharge, dynamic power down off */
str r1, [r0, #0x04] /* 芯片数量改为1 chip了*/
mov pc, lr
.if (CLK_400_200_166_133 == 1) || (CLK_800_200_166_133 == 1) || (CLK_1000_200_166_133 == 1)
.equ DMC0_MEMCONFIG_0, 0x30F01313 //配置DMC0上的第1个DDR芯片，当地址高位为0x3x时，打开片选Xm0cs0，
//1313表示linterleaved，[11:8]=3表示行地址10bit，[7:4]=1列地址13bit，最后的3表示8bank，那么Xm0CS1被设置为BA3，
//不再作为片选功能
//memconfig0 256MB config, 8 banks, mapping method[12:15] 0:linear, 1:linterleaved, 2:mixed */
//
.equ DMC0_MEMCONFIG_1, 0x40F01323 //配置DMC0上的第2个DDR芯片，当地址高位为0x4x时，打开片选Xm0cs1，实际上不可用，后面会关闭掉这个chip
//1323表示linterleaved，行地址10bit 列地址14bit 8bank，实际上后面会关闭掉这个chip，这句代码无效
.equ DMC0_TIMINGA_REF, 0x00000618
.equ DMC0_TIMING_ROW, 0x28233287
.equ DMC0_TIMING_DATA, 0x23240304
.equ DMC0_TIMING_PWR, 0x09C80232
.equ DMC1_MEMCONFIG_0, 0x40F01313 //配置DMC1上的第1个DDR芯片，当地址高位为0x3x时，打开片选Xm1cs0
.equ DMC1_MEMCONFIG_1, 0x00E01323 //配置DMC1上的第2个DDR芯片，当地址高位为0x4x时，打开片选Xm1cs1，实际上后面会关闭掉这个chip，这句代码无效
.equ DMC1_TIMINGA_REF, 0x00000618
.equ DMC1_TIMING_ROW, 0x28233289
.equ DMC1_TIMING_DATA, 0x23240304
.equ DMC1_TIMING_PWR, 0x08280232
.endif

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