169 #define LCD_LEFT_MARGIN 199
170 #define LCD_HSYNC_LEN 15
171 #define LCD_UPPER_MARGIN 1
172 #define LCD_LOWER_MARGIN 1
173 #define LCD_VSYNC_LEN 1
174 #define LCD_CON5 (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_HWSWP)
175
176 #elif defined(CONFIG_FB_S3C2410_X240320)
177 #define LCD_WIDTH 240
178 #define LCD_HEIGHT 320
179 #define LCD_PIXCLOCK 170000
180 #define LCD_RIGHT_MARGIN 25
181 #define LCD_LEFT_MARGIN 0
182 #define LCD_HSYNC_LEN 4
183 #define LCD_UPPER_MARGIN 0
184 #define LCD_LOWER_MARGIN 4
185 #define LCD_VSYNC_LEN 9
186 #define LCD_CON5 (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_INVVDEN | S3C2410_LCDCON5_INVVFRAME | S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_HWSWP )
187 #endif
188
189 #if defined (LCD_WIDTH)
190
191 static struct s3c2410fb_display mini2440_lcd_cfg __initdata = {
192 #if !defined (LCD_CON5)
193 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
194 S3C2410_LCDCON5_INVVLINE |
195 S3C2410_LCDCON5_INVVFRAME |
196 S3C2410_LCDCON5_PWREN |
197 S3C2410_LCDCON5_HWSWP,
198 #else
199 .lcdcon5 = LCD_CON5,
200 #endif
201 .type = S3C2410_LCDCON1_TFT,
202 .width = LCD_WIDTH,
203 .height = LCD_HEIGHT,
204 .pixclock = LCD_PIXCLOCK,
205 .xres = LCD_WIDTH,
206 .yres = LCD_HEIGHT,
207 .bpp = 16,
208 .left_margin = LCD_LEFT_MARGIN + 1,
209 .right_margin = LCD_RIGHT_MARGIN + 1,
210 .hsync_len = LCD_HSYNC_LEN + 1,
211 .upper_margin = LCD_UPPER_MARGIN + 1,
212 .lower_margin = LCD_LOWER_MARGIN + 1,
213 .vsync_len = LCD_VSYNC_LEN + 1,
214 };
215
216 static struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
217 .displays = &mini2440_lcd_cfg,
218 .num_displays = 1,
219 .default_display = 0,
220 .gpccon = 0xaa955699,
221 .gpccon_mask = 0xffc003cc,
222 .gpcup = 0x0000ffff,
223 .gpcup_mask = 0xffffffff,
224 .gpdcon = 0xaa95aaa1,
225 .gpdcon_mask = 0xffc0fff0,
226 .gpdup = 0x0000faff,
227 .gpdup_mask = 0xffffffff,
228 .lpcsel = 0xf82,
229 };
230
231 #endif
232