AM335x [uboot]调试DDR时序参数

本文基于 am335x-evm
uboot版本为 u-boot-2014.07




uboot中 ddr初始化在s_init函数中，该函数在 ：\board-support\u-boot-2014.07-g7e537bf\arch\arm\cpu\armv7\am33xx\board.c中
它调用config_ddr 函数进行初始化操作，
config_ddr() 定义在  arch\arm\cpu\armv7\am33xx\emif4.c 中

void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr)
{
ddr_pll_config(pll);
#ifndef CONFIG_TI81XX
/*
* If coming from a warm reset, skip the vtp configuration. This
* reg is warm reset insensitive.
*/
if (!(readl(&prm_device->prm_rstst) & PRM_RSTST_WARM_RESET_MASK))
config_vtp(nr);
else
writel(readl(&prm_device->prm_rstst) | PRM_RSTST_WARM_RESET_MASK,
      &prm_device->prm_rstst);
#endif
config_cmd_ctrl(ctrl, nr);


config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
config_io_ctrl(ioregs);


/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);


#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;


config_io_ctrl(ioregs);     //将ioctrl值写入 0x44e1 1404 ~ 0x44e1 1444 ddr_cmd0_ioctrl等


/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);


if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
/* Allow EMIF to control DDR_RESET */
writel(0x00000000, &ddrctrl->ddrioctrl);
#endif


/* Program EMIF instance */
config_ddr_phy(regs, nr);
set_sdram_timings(regs, nr);
if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
config_sdram_emif4d5(regs, nr);
else
config_sdram(regs, nr);
}

#endif
参数解析：  
int nr： 选择哪个phy控制器，默认为0
ddr_pll_config(); 函数
config_cmd_ctrl ， 初始化 DDR2/3/mDDR PHY 寄存器的cmd控制部分，地址为：0x44E1_2000 ~ 0x44e1 20c8
config_ddr_data，初始化 DDR2/3/mDDR PHY 寄存器的data部分。地址为：0x44E120C8 ~ 0x44e12120 
config_io_ctrl 函数对ddr控制器操作，地址为：0x44e1 1404~ 0x44e1 1444 wince中对这些寄存器写入 0x18B
config_ddr_phy(regs, nr); 操作emif寄存器中的DDR_PHY_CTRL_1，对应 0x4c00 00e4
set_sdram_timings(regs, nr); 操作timg
config_sdram(regs, nr);


移植时，在sdram_init()中添加目标板ddr初始化代码，这里贴上ISSI的 IS43TR16640 128M ddr3的初始化参数

#define IS43TR16640A15GBLI_EMIF_READ_LATENCY    0x000006    //0x44c0 00e4 ~ 0x44c0 00e8
#define IS43TR16640A15GBLI_EMIF_TIM1     0x0888a39b     //0x44c0 0018
#define IS43TR16640A15GBLI_EMIF_TIM2     0x26337fda     //0x44c0 0020
#define IS43TR16640A15GBLI_EMIF_TIM3     0x501f830f     //0x44c0 0028
#define IS43TR16640A15GBLI_EMIF_SDCFG     0x61c04ab2     //0x44c0 0008
#define IS43TR16640A15GBLI_EMIF_SDREF     0x0000093b     //0x44c0 0010
#define IS43TR16640A15GBLI_ZQ_CFG     0x50074BE4     //0x44c0 00c8
#define IS43TR16640A15GBLI_RATIO     0x40     //0x44e1 2000 ~ 0x44e1 20c8
#define IS43TR16640A15GBLI_INVERT_CLKOUT     0x01     //0x44e1 2000 ~ 0x44e1 20c8
#define IS43TR16640A15GBLI_RD_DQS     0x3b     //0x44e1 20c8
#define IS43TR16640A15GBLI_WR_DQS     0x85 //0x44e1 20dc
#define IS43TR16640A15GBLI_PHY_WRLVL     0x00       //ddr2 used
#define IS43TR16640A15GBLI_PHY_GATELVL     0x00     //ddr2 used
#define IS43TR16640A15GBLI_PHY_WR_DATA     0xc1     //0x44e1 2120
#define IS43TR16640A15GBLI_PHY_FIFO_WE     0x100     //0x44e1 2108
#define IS43TR16640A15GBLI_IOCTRL_VALUE     0x18B     //0x44e1 1404 ~ 0x44e1 1444


// ----------------------------------------------------------------
// define zy ddr3  IS43DR16640A-15GBLI
static const struct ddr_data ddr3_IS43DR1664_data = {
.datardsratio0 = IS43TR16640A15GBLI_RD_DQS,
.datawdsratio0 = IS43TR16640A15GBLI_WR_DQS,
.datafwsratio0 = IS43TR16640A15GBLI_PHY_FIFO_WE,
.datawrsratio0 = IS43TR16640A15GBLI_PHY_WR_DATA,
};


static const struct cmd_control ddr3_IS43DR1664_cmd_ctrl_data = {
.cmd0csratio = IS43TR16640A15GBLI_RATIO,
.cmd0iclkout = IS43TR16640A15GBLI_INVERT_CLKOUT,
.cmd1csratio = IS43TR16640A15GBLI_RATIO,
.cmd1iclkout = IS43TR16640A15GBLI_INVERT_CLKOUT,
.cmd2csratio = IS43TR16640A15GBLI_RATIO,
.cmd2iclkout = IS43TR16640A15GBLI_INVERT_CLKOUT,
};
static struct emif_regs ddr3_IS43DR1664_emif_reg_data = {
.sdram_config = IS43TR16640A15GBLI_EMIF_SDCFG,
.ref_ctrl = IS43TR16640A15GBLI_EMIF_SDREF,
.sdram_tim1 = IS43TR16640A15GBLI_EMIF_TIM1,
.sdram_tim2 = IS43TR16640A15GBLI_EMIF_TIM2,
.sdram_tim3 = IS43TR16640A15GBLI_EMIF_TIM3,
.zq_config = IS43TR16640A15GBLI_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = IS43TR16640A15GBLI_EMIF_READ_LATENCY/* |PHY_EN_DYN_PWRDN*/,
};
// ----------------------------------------------------------------

完成修改后，重新编译生成MLO文件，即可看到uboot中的串口输出信息了，系统已经能够在内存中欢腾的运行