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OK6410（256M RAM ，1G SLC NAND）Uboot-2013-04移植（5）--NAND卡启动

分类： 嵌入式

2014-04-06 17:38:39

1.修改include/configs/smdk6410.h，更改nandflash大小，改为

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  1. /* NAND chip page size */
  2. #define CONFIG_SYS_NAND_PAGE_SIZE 4096
  3. /* NAND chip block size */
  4. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  5. /* NAND chip page per block count */
  6. #define CONFIG_SYS_NAND_PAGE_COUNT 128


2.支持8位ECC

    替换drivers/mtd/nand/s3c64xx.c，替换文件下载地址：，内容如下

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  1. /*
  2.  * (C) Copyright 2006 DENX Software Engineering
  3.  *
  4.  * Implementation for U-Boot 1.1.6 by Samsung
  5.  *
  6.  * (C) Copyright 2008
  7.  * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  8.  *
  9.  * See file CREDITS for list of people who contributed to this
  10.  * project.
  11.  *
  12.  * This program is free software; you can redistribute it and/or
  13.  * modify it under the terms of the GNU General Public License as
  14.  * published by the Free Software Foundation; either version 2 of
  15.  * the License, or (at your option) any later version.
  16.  *
  17.  * This program is distributed in the hope that it will be useful,
  18.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20.  * GNU General Public License for more details.
  21.  *
  22.  * You should have received a copy of the GNU General Public License
  23.  * along with this program; if not, write to the Free Software
  24.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25.  * MA 02111-1307 USA
  26.  */

  28. #include <common.h>

  30. #include <nand.h>
  31. #include <linux/mtd/nand.h>

  33. #ifdef CONFIG_S3C6400
  34. #include <asm/arch/s3c6400.h>
  35. #else
  36. #include <asm/arch/s3c6410.h>
  37. #endif

  39. #include <asm/io.h>
  40. #include <asm/errno.h>

  42. #define MAX_CHIPS    2
  43. static int nand_cs[MAX_CHIPS] = {0, 1};

  45. #ifdef CONFIG_NAND_SPL
  46. #define printf(arg...) do {} while (0)
  47. #endif

  49. /* Nand flash definition values by jsgood */
  50. #ifdef S3C_NAND_DEBUG
  51. /*
  52.  * Function to print out oob buffer for debugging
  53.  * Written by jsgood
  54.  */
  55. static void print_oob(const char *header, struct mtd_info *mtd)
  56. {
  57.     int i;
  58.     struct nand_chip *chip = mtd->priv;

  60.     printf("%s:\t", header);

  62.     for (i = 0; i < 64; i++)
  63.         printf("%02x ", chip->oob_poi[i]);

  65.     printf("\n");
  66. }
  67. #endif /* S3C_NAND_DEBUG */

  69. static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
  70. {
  71.     int ctrl = readl(NFCONT);

  73.     switch (chip) {
  74.     case -1:
  75.         ctrl |= 6;
  76.         break;
  77.     case 0:
  78.         ctrl &= ~2;
  79.         break;
  80.     case 1:
  81.         ctrl &= ~4;
  82.         break;
  83.     default:
  84.         return;
  85.     }

  87.     writel(ctrl, NFCONT);
  88. }

  90. /*
  91.  * Hardware specific access to control-lines function
  92.  * Written by jsgood
  93.  */
  94. static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  95. {
  96.     struct nand_chip *this = mtd->priv;

  98.     if (ctrl & NAND_CTRL_CHANGE) {
  99.         if (ctrl & NAND_CLE)
  100.             this->IO_ADDR_W = (void __iomem *)NFCMMD;
  101.         else if (ctrl & NAND_ALE)
  102.             this->IO_ADDR_W = (void __iomem *)NFADDR;
  103.         else
  104.             this->IO_ADDR_W = (void __iomem *)NFDATA;
  105.         if (ctrl & NAND_NCE)
  106.             s3c_nand_select_chip(mtd, *(int *)this->priv);
  107.         else
  108.             s3c_nand_select_chip(mtd, -1);
  109.     }

  111.     if (cmd != NAND_CMD_NONE)
  112.         writeb(cmd, this->IO_ADDR_W);
  113. }

  115. /*
  116.  * Function for checking device ready pin
  117.  * Written by jsgood
  118.  */
  119. static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
  120. {
  121.     return !!(readl(NFSTAT) & NFSTAT_RnB);
  122. }

  124. #ifdef CONFIG_SYS_S3C_NAND_HWECC
  125. /*
  126.  * This function is called before encoding ecc codes to ready ecc engine.
  127.  * Written by jsgood
  128.  */
  129.  
  130. #if defined(CONFIG_NAND_BL1_8BIT_ECC) && (defined(CONFIG_S3C6410) || defined(CONFIG_S3C6430))
  131.  /***************************************************************
  132.   * jsgood: Temporary 8 Bit H/W ECC supports for BL1 (6410/6430 only)
  133.   ***************************************************************/
  134.  int cur_ecc_mode=0;
  135.     /*
  136.      * Function for checking ECCEncDone in NFSTAT
  137.      * Written by jsgood
  138.      */
  139.     static void s3c_nand_wait_enc(void)
  140.     {
  141.         while (!(readl(NFSTAT) & NFSTAT_ECCENCDONE)) {}
  142.     }
  143.     
  144.     /*
  145.      * Function for checking ECCDecDone in NFSTAT
  146.      * Written by jsgood
  147.      */
  148.     static void s3c_nand_wait_dec(void)
  149.     {
  150.         while (!(readl(NFSTAT) & NFSTAT_ECCDECDONE)) {}
  151.     }
  152.   
  153.  static void s3c_nand_wait_ecc_busy_8bit(void)
  154.  {
  155.      while (readl(NF8ECCERR0) & NFESTAT0_ECCBUSY) {}
  156.  }
  157.  void s3c_nand_enable_hwecc_8bit(struct mtd_info *mtd, int mode)
  158. {
  159.     u_long nfcont, nfconf;

  161.     cur_ecc_mode = mode;

  163.     /* 8 bit selection */
  164.     nfconf = readl(NFCONF);

  166.     nfconf &= ~(0x3 << 23);
  167.     nfconf |= (0x1 << 23);

  169.     writel(nfconf, NFCONF);

  171.     /* Initialize & unlock */
  172.     nfcont = readl(NFCONT);
  173.     nfcont |= NFCONT_INITECC;
  174.     nfcont &= ~NFCONT_MECCLOCK;

  176.     if (mode == NAND_ECC_WRITE)
  177.         nfcont |= NFCONT_ECC_ENC;
  178.     else if (mode == NAND_ECC_READ)
  179.         nfcont &= ~NFCONT_ECC_ENC;

  181.     writel(nfcont, NFCONT);
  182. }
  183. int s3c_nand_calculate_ecc_8bit(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
  184. {
  185.     u_long nfcont, nfm8ecc0, nfm8ecc1, nfm8ecc2, nfm8ecc3;

  187.     /* Lock */
  188.     nfcont = readl(NFCONT);
  189.     nfcont |= NFCONT_MECCLOCK;
  190.     writel(nfcont, NFCONT);

  192.     if (cur_ecc_mode == NAND_ECC_READ)
  193.         s3c_nand_wait_dec();
  194.     else {
  195.         s3c_nand_wait_enc();

  197.         nfm8ecc0 = readl(NFM8ECC0);
  198.         nfm8ecc1 = readl(NFM8ECC1);
  199.         nfm8ecc2 = readl(NFM8ECC2);
  200.         nfm8ecc3 = readl(NFM8ECC3);

  202.         ecc_code[0] = nfm8ecc0 & 0xff;
  203.         ecc_code[1] = (nfm8ecc0 >> 8) & 0xff;
  204.         ecc_code[2] = (nfm8ecc0 >> 16) & 0xff;
  205.         ecc_code[3] = (nfm8ecc0 >> 24) & 0xff;
  206.         ecc_code[4] = nfm8ecc1 & 0xff;
  207.         ecc_code[5] = (nfm8ecc1 >> 8) & 0xff;
  208.         ecc_code[6] = (nfm8ecc1 >> 16) & 0xff;
  209.         ecc_code[7] = (nfm8ecc1 >> 24) & 0xff;
  210.         ecc_code[8] = nfm8ecc2 & 0xff;
  211.         ecc_code[9] = (nfm8ecc2 >> 8) & 0xff;
  212.         ecc_code[10] = (nfm8ecc2 >> 16) & 0xff;
  213.         ecc_code[11] = (nfm8ecc2 >> 24) & 0xff;
  214.         ecc_code[12] = nfm8ecc3 & 0xff;
  215.     }

  217.     return 0;
  218. }

  220. int s3c_nand_correct_data_8bit(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
  221. {
  222.     int ret = -1;
  223.     u_long nf8eccerr0, nf8eccerr1, nf8eccerr2, nfmlc8bitpt0, nfmlc8bitpt1;
  224.     u_char err_type;

  226.     s3c_nand_wait_ecc_busy_8bit();

  228.     nf8eccerr0 = readl(NF8ECCERR0);
  229.     nf8eccerr1 = readl(NF8ECCERR1);
  230.     nf8eccerr2 = readl(NF8ECCERR2);
  231.     nfmlc8bitpt0 = readl(NFMLC8BITPT0);
  232.     nfmlc8bitpt1 = readl(NFMLC8BITPT1);

  234.     err_type = (nf8eccerr0 >> 25) & 0xf;

  236.     /* No error, If free page (all 0xff) */
  237.     if ((nf8eccerr0 >> 29) & 0x1)
  238.         err_type = 0;

  240.     switch (err_type)
  241.     {
  242.     case 8: /* 8 bit error (Correctable) */
  243.         dat[(nf8eccerr2 >> 22) & 0x3ff] ^= ((nfmlc8bitpt1 >> 24) & 0xff);
  244.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);

  246.     case 7: /* 7 bit error (Correctable) */
  247.         dat[(nf8eccerr2 >> 11) & 0x3ff] ^= ((nfmlc8bitpt1 >> 16) & 0xff);
  248.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);

  250.     case 6: /* 6 bit error (Correctable) */
  251.         dat[nf8eccerr2 & 0x3ff] ^= ((nfmlc8bitpt1 >> 8) & 0xff);
  252.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);

  254.     case 5: /* 5 bit error (Correctable) */
  255.         dat[(nf8eccerr1 >> 22) & 0x3ff] ^= (nfmlc8bitpt1 & 0xff);
  256.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);

  258.     case 4: /* 4 bit error (Correctable) */
  259.         dat[(nf8eccerr1 >> 11) & 0x3ff] ^= ((nfmlc8bitpt0 >> 24) & 0xff);
  260.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);

  262.     case 3: /* 3 bit error (Correctable) */
  263.         dat[nf8eccerr1 & 0x3ff] ^= ((nfmlc8bitpt0 >> 16) & 0xff);
  264.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);

  266.     case 2: /* 2 bit error (Correctable) */
  267.         dat[(nf8eccerr0 >> 15) & 0x3ff] ^= ((nfmlc8bitpt0 >> 8) & 0xff);
  268.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);


  271.     case 1: /* 1 bit error (Correctable) */
  272.         printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);
  273.         dat[nf8eccerr0 & 0x3ff] ^= (nfmlc8bitpt0 & 0xff);
  274.         ret = err_type;
  275.         break;

  277.     case 0: /* No error */
  278.         ret = 0;
  279.         break;

  281.     }

  283.     return ret;
  284. }

  286. void s3c_nand_write_page_8bit(struct mtd_info *mtd, struct nand_chip *chip,
  287.                               const uint8_t *buf)
  288. {
  289.     int i, eccsize = 512;
  290.     int eccbytes = 13;
  291.     int eccsteps = mtd->writesize / eccsize;
  292.     uint8_t *ecc_calc = chip->buffers->ecccalc;
  293.     uint8_t *p = buf;

  295.     for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  296.         s3c_nand_enable_hwecc_8bit(mtd, NAND_ECC_WRITE);
  297.         chip->write_buf(mtd, p, eccsize);
  298.         s3c_nand_calculate_ecc_8bit(mtd, p, &ecc_calc[i]);
  299.     }

  301.     for (i = 0; i < eccbytes * (mtd->writesize / eccsize); i++)
  302.         chip->oob_poi[i+24] = ecc_calc[i];
  303.     chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  304. }

  306. int s3c_nand_read_page_8bit(struct mtd_info *mtd, struct nand_chip *chip,
  307.                             uint8_t *buf)
  308. {
  309.     int i, stat, eccsize = 512;
  310.     int eccbytes = 13;
  311.     int eccsteps = mtd->writesize / eccsize;
  312.     int col = 0;
  313.     uint8_t *p = buf;

  315.     /* Step1: read whole oob */
  316.     col = mtd->writesize;
  317.     chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
  318.     chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);

  320.     col = 0;
  321.     for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  322.         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
  323.         s3c_nand_enable_hwecc_8bit(mtd, NAND_ECC_READ);
  324.         chip->read_buf(mtd, p, eccsize);
  325.         chip->write_buf(mtd, chip->oob_poi + 24 + (((mtd->writesize / eccsize) - eccsteps) * eccbytes), eccbytes);
  326.         s3c_nand_calculate_ecc_8bit(mtd, 0, 0);
  327.         stat = s3c_nand_correct_data_8bit(mtd, p, 0, 0);

  329.         if (stat == -1)
  330.             mtd->ecc_stats.failed++;

  332.         col = eccsize * ((mtd->writesize / eccsize) + 1 - eccsteps);
  333.     }

  335.     return 0;
  336. }

  338. /********************************************************/
  339. #endif

  341. static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  342. {
  343.     u_long nfcont, nfconf;

  345.     /*
  346.      * The original driver used 4-bit ECC for "new" MLC chips, i.e., for
  347.      * those with non-zero ID[3][3:2], which anyway only holds for ST
  348.      * (Numonyx) chips
  349.      */

  351.     nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT;
  352.     
  353.     writel(nfconf, NFCONF);

  355.     /* Initialize & unlock */
  356.     nfcont = readl(NFCONT);
  357.     nfcont |= NFCONT_INITECC;
  358.     nfcont &= ~NFCONT_MECCLOCK;

  360.     if (mode == NAND_ECC_WRITE)
  361.         nfcont |= NFCONT_ECC_ENC;
  362.     else if (mode == NAND_ECC_READ)
  363.         nfcont &= ~NFCONT_ECC_ENC;

  365.     writel(nfcont, NFCONT);
  366. }

  368. /*
  369.  * This function is called immediately after encoding ecc codes.
  370.  * This function returns encoded ecc codes.
  371.  * Written by jsgood
  372.  */
  373. static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  374.                  u_char *ecc_code)
  375. {
  376.     u_long nfcont, nfmecc0;
  377.     /* Lock */
  378.     nfcont = readl(NFCONT);
  379.     nfcont |= NFCONT_MECCLOCK;
  380.     writel(nfcont, NFCONT);

  382.     nfmecc0 = readl(NFMECC0);

  384.     ecc_code[0] = nfmecc0 & 0xff;
  385.     ecc_code[1] = (nfmecc0 >> 8) & 0xff;
  386.     ecc_code[2] = (nfmecc0 >> 16) & 0xff;
  387.     ecc_code[3] = (nfmecc0 >> 24) & 0xff;
  388.     
  389.     return 0;
  390. }

  392. /*
  393.  * This function determines whether read data is good or not.
  394.  * If SLC, must write ecc codes to controller before reading status bit.
  395.  * If MLC, status bit is already set, so only reading is needed.
  396.  * If status bit is good, return 0.
  397.  * If correctable errors occured, do that.
  398.  * If uncorrectable errors occured, return -1.
  399.  * Written by jsgood
  400.  */
  401. static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  402.                  u_char *read_ecc, u_char *calc_ecc)
  403. {
  404.     int ret = -1;
  405.     u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr;
  406.     u_char err_type, repaired;

  408.     /* SLC: Write ecc to compare */
  409.     nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
  410.     nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
  411.     writel(nfmeccdata0, NFMECCDATA0);
  412.     writel(nfmeccdata1, NFMECCDATA1);

  414.     /* Read ecc status */
  415.     nfestat0 = readl(NFESTAT0);
  416.     err_type = nfestat0 & 0x3;

  418.     switch (err_type) {
  419.     case 0: /* No error */
  420.         ret = 0;
  421.         break;

  423.     case 1:
  424.         /*
  425.          * 1 bit error (Correctable)
  426.          * (nfestat0 >> 7) & 0x7ff    :error byte number
  427.          * (nfestat0 >> 4) & 0x7    :error bit number
  428.          */
  429.         err_byte_addr = (nfestat0 >> 7) & 0x7ff;
  430.         repaired = dat[err_byte_addr] ^ (1 << ((nfestat0 >> 4) & 0x7));

  432.         printf("S3C NAND: 1 bit error detected at byte %ld. "
  433.          "Correcting from 0x%02x to 0x%02x...OK\n",
  434.          err_byte_addr, dat[err_byte_addr], repaired);

  436.         dat[err_byte_addr] = repaired;

  438.         ret = 1;
  439.         break;

  441.     case 2: /* Multiple error */
  442.     case 3: /* ECC area error */
  443.         printf("S3C NAND: ECC uncorrectable error detected. "
  444.          "Not correctable.\n");
  445.         ret = -1;
  446.         break;
  447.     }

  449.     return ret;
  450. }
  451. #endif /* CONFIG_SYS_S3C_NAND_HWECC */

  453. /*
  454.  * Board-specific NAND initialization. The following members of the
  455.  * argument are board-specific (per include/linux/mtd/nand.h):
  456.  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  457.  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
  458.  * - hwcontrol: hardwarespecific function for accesing control-lines
  459.  * - dev_ready: hardwarespecific function for accesing device ready/busy line
  460.  * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
  461.  * only be provided if a hardware ECC is available
  462.  * - eccmode: mode of ecc, see defines
  463.  * - chip_delay: chip dependent delay for transfering data from array to
  464.  * read regs (tR)
  465.  * - options: various chip options. They can partly be set to inform
  466.  * nand_scan about special functionality. See the defines for further
  467.  * explanation
  468.  * Members with a "?" were not set in the merged testing-NAND branch,
  469.  * so they are not set here either.
  470.  */
  471. int board_nand_init(struct nand_chip *nand)
  472. {
  473.     static int chip_n;

  475.     if (chip_n >= MAX_CHIPS)
  476.         return -ENODEV;

  478.     NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6;

  480.     nand->IO_ADDR_R        = (void __iomem *)NFDATA;
  481.     nand->IO_ADDR_W        = (void __iomem *)NFDATA;
  482.     nand->cmd_ctrl        = s3c_nand_hwcontrol;
  483.     nand->dev_ready        = s3c_nand_device_ready;
  484.     nand->select_chip    = s3c_nand_select_chip;
  485.     nand->options        = 0;
  486. #ifdef CONFIG_NAND_SPL
  487.     nand->read_byte        = nand_read_byte;
  488.     nand->write_buf        = nand_write_buf;
  489.     nand->read_buf        = nand_read_buf;
  490. #endif

  492. #ifdef CONFIG_SYS_S3C_NAND_HWECC
  493.     #ifdef CONFIG_NAND_BL1_8BIT_ECC
  494.     printf("USE HWECC 8BIT\n");//zxd
  495.     nand->ecc.hwctl        = s3c_nand_enable_hwecc_8bit;
  496.     nand->ecc.calculate    = s3c_nand_calculate_ecc_8bit;
  497.     nand->ecc.correct    = s3c_nand_correct_data_8bit;
  498.     nand->ecc.read_page = s3c_nand_read_page_8bit;
  499.     nand->ecc.write_page = s3c_nand_write_page_8bit;
  500.     #else
  501.     printf("USE HWECC Default\n");//zxd
  502.     nand->ecc.hwctl        = s3c_nand_enable_hwecc;
  503.     nand->ecc.calculate    = s3c_nand_calculate_ecc;
  504.     nand->ecc.correct    = s3c_nand_correct_data;
  505.     #endif
  506.     /*
  507.      * If you get more than 1 NAND-chip with different page-sizes on the
  508.      * board one day, it will get more complicated...
  509.      */
  510.     nand->ecc.mode        = NAND_ECC_HW;
  511.     nand->ecc.size        = CONFIG_SYS_NAND_ECCSIZE;
  512.     nand->ecc.bytes        = CONFIG_SYS_NAND_ECCBYTES;
  513.     printf("ECC Size:%d ECC Bytes:%d\n",nand->ecc.size,nand->ecc.bytes);//zxd    
  514. #else
  515.     nand->ecc.mode        = NAND_ECC_SOFT;
  516. #endif /* ! CONFIG_SYS_S3C_NAND_HWECC */

  518.     nand->priv        = nand_cs + chip_n++;

  520.     return 0;
  521. }

    修改common/cmd_nand.c文件，在662行的#endif之后、#ifdef CONFIG_CMD_NAND_YAFFS之前添加

点击(此处)折叠或打开

  1. } else if (!read && s != NULL && (!strcmp(s, ".uboot")) && nand->writesize == 4096) {
  2.                 rwsize=4096;
  3.                 nand_write(nand, off, &rwsize, (u_char *)addr);
  4.                 off+=4096;
  5.                 addr+=2048;
  6.                 nand_write(nand, off, &rwsize, (u_char *)addr);
  7.                 off+=4096;
  8.                 addr+=2048;
  9.                 nand_write(nand, off, &rwsize, (u_char *)addr);
  10.                 off+=4096;
  11.                 addr+=2048;
  12.                 nand_write(nand, off, &rwsize, (u_char *)addr);
  13.                 off+=4096;
  14.                 addr+=2048;
  15.                 rwsize= CONFIG_SYS_NAND_U_BOOT_SIZE - 8*1024;
  16.                 ret = nand_write(nand, off, &rwsize, (u_char *)addr);

    修改nand_spl/board/samsung/smdk6410/cinfig.mk，把PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096])
                改为PAD_TO := $(shell expr $CONFIG_SYS_TEXT_BASE) + 8192)


3.制作SD卡启动的u-boot.bin，修改include/configs/smdk6410.h，把

点击(此处)折叠或打开

  1. #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
  2. #define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
  3.                             "bootm 0x50018000"
  4. #endif
    修改为

点击(此处)折叠或打开

  1. #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
  2. #ifdef CONFIG_BOOT_SD
  3. #define CONFIG_BOOTCOMMAND "fatload mmc 0 50008000 u-boot-nand.bin;" \
  4.                             "nand erase.chip;" \
  5.                             "nand write.uboot 50008000 0 0"
  6. #else
  7. #define CONFIG_BOOTCOMMAND "nand read 0x50008000 0x100000 0x500000;" \
  8.                             "bootm 50008000"
  9. #endif
  10. #endif
    把生成的u-boot.bin烧写到SD卡，这样开发板SD卡启动后会执行fatload mmc 0 50008000 u-boot-nand.bin;""nand erase.chip;" "nand write.uboot 50008000 0 0"三个命令


4.修改include/configs/smdk6410.h，注释掉#define CONFIG_BOOT_SD

    修改

点击(此处)折叠或打开

  1. #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 * 1024) /* Offset to RAM U-Boot image */
  2. #define CONFIG_SYS_NAND_U_BOOT_SIZE (496 * 1024) /* Size of RAM U-Boot image */


    修改board/samsung/smdk6410/smdk6410_nand_spl.c，把relocate_code(CONFIG_SYS_TEXT_BASE -TOTAL_MALLOC_LEN, NULL,CONFIG_SYS_TEXT_BASE);修改为relocate_code(8*1024, NULL,CONFIG_SYS_TEXT_BASE);

    修改arch/arm/lib/crt0.S，在

点击(此处)折叠或打开

  1. #if defined(CONFIG_NAND_SPL)
  2. /* deprecated, use instead CONFIG_SPL_BUILD */
  3. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  4. 后面添加
  5. bss_clean:
  6. cmp r0,r1
  7. strlo r2,[r0]
  8. addlo r0,r0,#4
  9. blo bss_clean
  10. ldr pc,=nand_boot


5.制作NAND启动的u-boot-nand.bin，重新make all，把u-boot-nand.bin拷贝到刚刚烧写了u-boot.bin的SD卡中，SD卡启动开发板，自动将u-boot-nand.bin写入到nandflash中，结果如下

    
    再把开发板拨到nandflash启动，结果如下，开发板正常启动
     
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