UBOOT移植第一阶段源码

@***************************
  2 @File:start.S
  3 @***************************
  4
  5 .text
  6 .global _start
  7 _start:
  8         b   reset
  9         ldr pc, _undefined_instruction
 10         ldr pc, _software_interrupt
 11         ldr pc, _prefetch_abort
 12         ldr pc, _data_abort
 13         ldr pc, _not_used
 14         ldr pc, _irq
 15         ldr pc, _fiq
 16
 17 _undefined_instruction: .word undefined_instruction
 18 _software_interrupt: .word software_interrupt
 19 _prefetch_abort: .word prefetch_abort
 20 _data_abort: .word data_abort
 21 _not_used: .word not_used
22 _irq: .word irq
 23 _fiq: .word fiq
 24 undefined_instruction:
 25             nop
 26 software_interrupt:
 27             nop
 28 prefetch_abort:
 29             nop
 30 data_abort:
 31             nop
 32 not_used:
 33         nop
 34 irq:
 35     nop
 36 fiq:
 37     nop
 38 reset:
 39     bl set_svc
 40     bl disable_watchdog
 41     bl disable_interrupt
 42     bl disable_mmu
 43     bl clock_init
 44     bl init_sdram
 45     bl copy_to_ram
 46     bl init_stack
 47     bl clean_bss
 48     ldr pc, =main
 49 @   bl led
 50 set_svc:
 51     mrs r0, cpsr
 52     bic r0, r0, #0x1f
 53     orr r0, r0, #0xd3
 54     msr cpsr, r0
 55     mov pc, lr
 56 disable_watchdog:
 57     ldr r0, =0x53000000
 58     mov r1, #0x0
 59     str r1, [r0]
 60     mov pc, lr
 61 disable_interrupt:
 62     mvn r1, #0x0
 63     ldr r0, =0x4a000008
 64     str r1, [r0]
65     mov pc, lr
 66 disable_mmu:
 67     mcr p15, 0, r0, c7, c7, 0
 68     mrc p15, 0, r0, c1, c0, 0
 69     bic r0, r0, #0x00000007
 70     mcr p15, 0, r0, c1, c0, 0
 71     mov pc, lr
 72
 73 #define MPLLCON 0x4c000004
 74 #define PLL_VALUE ((127<<12) | (2<<4) | (1<<0))
 75 clock_init:
 76     ldr r0, =0x4c000014
 77     mov r1, #0x5
 78     str r1, [r0]
 79
 80     mrc p15, 0, r0, c1, c0, 0
 81     orr r0, r0, #0xc0000000
 82     mcr p15, 0, r0, c1, c0, 0
 83
 84     ldr r0, =MPLLCON
 85     ldr r1, =PLL_VALUE
 86     str r1, [r0]
 87     mov pc, lr
 88 #define men_ctrl 0x48000000
 89 init_sdram:
 90      ldr r0, =men_ctrl
 91      add r1, r0, #4*13
 92      adrl r2, men_data
 93 0:
 94      ldr r3, [r2],#4
 95      str r3, [r0],#4
 96      cmp r0, r1
 97      bne 0b
 98
 99 men_data:
100     .long 0x22000000
101     .long 0x00000700
102     .long 0x00000700
103     .long 0x00000700
104     .long 0x00000700
105     .long 0x00000700
106     .long 0x00000700
107     .long 0x00000700
108     .long 0x00018001
109     .long 0x00018001
110     .long 0x008c04f5
111     .long 0x000000b1
112     .long 0x00000030
113     .long 0x00000030
114
115     mov pc, lr
116 copy_to_ram:
117     ldr r0, =0x0
118     ldr r1, =0x30008000
119     add r2, r1, #1024*4
120 copy_code:
121     ldr r3, [r0], #4
122     str r3, [r1], #4
123     cmp r1, r2
124     bne copy_code
125
126     mov pc, lr
127 init_stack:
128     ldr sp, =0x34000000
129     mov pc, lr
130 clean_bss:
131     ldr r0, =bss_start
132     ldr r1, =bss_end
133     cmp r0, r1
134     moveq pc,lr
135 clean_loop:
136     mov r2, #0x0
137     str r2, [r0], #4
138     cmp r0, r1
139     bne clean_loop
140     mov pc, lr
141 led:
142     ldr r0, =0x56000010
143     mov r1, #0x400
144     str r1, [r0]
145
146     ldr r0, =0x56000014
147     mov r1, #0x0
148     str r1, [r0]
149     mov pc, lr
150
151
152