/* linux/include/asm-arm/arch-s3c2410/regs-hsmmc.h
*
* Copyright (c) 2004 Samsung Electronics
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C HS-MMC Controller
*/
#ifndef __ASM_ARCH_REGS_HSMMC_H
#define __ASM_ARCH_REGS_HSMMC_H __FILE__
/*
* HS MMC Interface
*/
#define S3C_HSMMC_REG(x) (x)
#define S3C_HSMMC_SYSAD (0x00)
#define S3C_HSMMC_BLKSIZE (0x04)
#define S3C_HSMMC_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
#define S3C_HSMMC_BLKCNT (0x06)
#define S3C_HSMMC_ARGUMENT (0x08)
#define S3C_HSMMC_TRNMOD (0x0c)
#define S3C_HSMMC_TRNS_DMA 0x01
#define S3C_HSMMC_TRNS_BLK_CNT_EN 0x02
#define S3C_HSMMC_TRNS_ACMD12 0x04
#define S3C_HSMMC_TRNS_READ 0x10
#define S3C_HSMMC_TRNS_MULTI 0x20
#define S3C_HSMMC_CMDREG (0x0e)
#define S3C_HSMMC_RSPREG0 (0x10)
#define S3C_HSMMC_RSPREG1 (0x14)
#define S3C_HSMMC_RSPREG2 (0x18)
#define S3C_HSMMC_RSPREG3 (0x1c)
#define S3C_HSMMC_CMD_RESP_MASK 0x03
#define S3C_HSMMC_CMD_CRC 0x08
#define S3C_HSMMC_CMD_INDEX 0x10
#define S3C_HSMMC_CMD_DATA 0x20
#define S3C_HSMMC_CMD_RESP_NONE 0x00
#define S3C_HSMMC_CMD_RESP_LONG 0x01
#define S3C_HSMMC_CMD_RESP_SHORT 0x02
#define S3C_HSMMC_CMD_RESP_SHORT_BUSY 0x03
#define S3C_HSMMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
#define S3C_HSMMC_BDATA (0x20)
#define S3C_HSMMC_PRNSTS (0x24)
#define S3C_HSMMC_CMD_INHIBIT 0x00000001
#define S3C_HSMMC_DATA_INHIBIT 0x00000002
#define S3C_HSMMC_DOING_WRITE 0x00000100
#define S3C_HSMMC_DOING_READ 0x00000200
#define S3C_HSMMC_SPACE_AVAILABLE 0x00000400
#define S3C_HSMMC_DATA_AVAILABLE 0x00000800
#define S3C_HSMMC_CARD_PRESENT 0x00010000
#define S3C_HSMMC_WRITE_PROTECT 0x00080000
#define S3C_HSMMC_HOSTCTL (0x28)
#define S3C_HSMMC_CTRL_LED 0x01
#define S3C_HSMMC_CTRL_4BITBUS 0x02
#define S3C_HSMMC_CTRL_HIGHSPEED 0x04
#define S3C_HSMMC_CTRL_1BIT 0x00
#define S3C_HSMMC_CTRL_4BIT 0x02
#define S3C_HSMMC_CTRL_8BIT 0x20
#define S3C_HSMMC_CTRL_SDMA 0x00
#define S3C_HSMMC_CTRL_ADMA2_32 0x10
#define S3C_HSMMC_PWRCON (0x29)
#define S3C_HSMMC_POWER_OFF 0x00
#define S3C_HSMMC_POWER_ON 0x01
#define S3C_HSMMC_POWER_180 0x0A
#define S3C_HSMMC_POWER_300 0x0C
#define S3C_HSMMC_POWER_330 0x0E
#define S3C_HSMMC_POWER_ON_ALL 0xFF
#define S3C_HSMMC_BLKGAP (0x2a)
#define S3C_HSMMC_WAKCON (0x2b)
#define S3C_HSMMC_CLKCON (0x2c)
#define S3C_HSMMC_DIVIDER_SHIFT 8
#define S3C_HSMMC_CLOCK_EXT_STABLE 0x0008
#define S3C_HSMMC_CLOCK_CARD_EN 0x0004
#define S3C_HSMMC_CLOCK_INT_STABLE 0x0002
#define S3C_HSMMC_CLOCK_INT_EN 0x0001
#define S3C_HSMMC_TIMEOUTCON (0x2e)
#define S3C_HSMMC_TIMEOUT_MAX 0x0E
#define S3C_HSMMC_SWRST (0x2f)
#define S3C_HSMMC_RESET_ALL 0x01
#define S3C_HSMMC_RESET_CMD 0x02
#define S3C_HSMMC_RESET_DATA 0x04
#define S3C_HSMMC_NORINTSTS (0x30)
#define S3C_HSMMC_NIS_ERR 0x00008000
#define S3C_HSMMC_NIS_CMDCMP 0x00000001
#define S3C_HSMMC_NIS_TRSCMP 0x00000002
#define S3C_HSMMC_NIS_DMA 0x00000008
#define S3C_HSMMC_ERRINTSTS (0x32)
#define S3C_HSMMC_EIS_CMDTIMEOUT 0x00000001
#define S3C_HSMMC_EIS_CMDERR 0x0000000E
#define S3C_HSMMC_EIS_DATATIMEOUT 0x00000010
#define S3C_HSMMC_EIS_DATAERR 0x00000060
#define S3C_HSMMC_EIS_CMD12ERR 0x00000100
#define S3C_HSMMC_EIS_ADMAERR 0x00000200
#define S3C_HSMMC_NORINTSTSEN (0x34)
#define S3C_HSMMC_ERRINTSTSEN (0x36)
#define S3C_HSMMC_NORINTSIGEN (0x38)
#define S3C_HSMMC_INT_MASK_ALL 0x0000
#define S3C_HSMMC_INT_RESPONSE 0x00000001
#define S3C_HSMMC_INT_DATA_END 0x00000002
#define S3C_HSMMC_INT_DMA_END 0x00000008
#define S3C_HSMMC_INT_SPACE_AVAIL 0x00000010
#define S3C_HSMMC_INT_DATA_AVAIL 0x00000020
#define S3C_HSMMC_INT_CARD_INSERT 0x00000040
#define S3C_HSMMC_INT_CARD_REMOVE 0x00000080
#define S3C_HSMMC_INT_CARD_CHANGE 0x000000c0 /* oring of above two */
#define S3C_HSMMC_INT_CARD_INT 0x00000100
#define S3C_HSMMC_INT_TIMEOUT 0x00010000
#define S3C_HSMMC_INT_CRC 0x00020000
#define S3C_HSMMC_INT_END_BIT 0x00040000
#define S3C_HSMMC_INT_INDEX 0x00080000
#define S3C_HSMMC_INT_DATA_TIMEOUT 0x00100000
#define S3C_HSMMC_INT_DATA_CRC 0x00200000
#define S3C_HSMMC_INT_DATA_END_BIT 0x00400000
#define S3C_HSMMC_INT_BUS_POWER 0x00800000
#define S3C_HSMMC_INT_ACMD12ERR 0x01000000
#define S3C_HSMMC_INT_ADMAERR 0x02000000
#define S3C_HSMMC_INT_NORMAL_MASK 0x00007FFF
#define S3C_HSMMC_INT_ERROR_MASK 0xFFFF8000
#define S3C_HSMMC_INT_CMD_MASK (S3C_HSMMC_INT_RESPONSE | \
S3C_HSMMC_INT_TIMEOUT | \
S3C_HSMMC_INT_CRC | \
S3C_HSMMC_INT_END_BIT | \
S3C_HSMMC_INT_INDEX | \
S3C_HSMMC_NIS_ERR \
)
#define S3C_HSMMC_INT_DATA_MASK (S3C_HSMMC_INT_DATA_END | \
S3C_HSMMC_INT_DMA_END | \
S3C_HSMMC_INT_DATA_AVAIL | \
S3C_HSMMC_INT_SPACE_AVAIL | \
S3C_HSMMC_INT_DATA_TIMEOUT | \
S3C_HSMMC_INT_DATA_CRC | \
S3C_HSMMC_INT_DATA_END_BIT \
)
#define S3C_HSMMC_ERRINTSIGEN (0x3a)
#define S3C_HSMMC_ACMD12ERRSTS (0x3c)
#define S3C_HSMMC_CAPAREG (0x40)
#define S3C_HSMMC_TIMEOUT_CLK_MASK 0x0000003F
#define S3C_HSMMC_TIMEOUT_CLK_SHIFT 0
#define S3C_HSMMC_TIMEOUT_CLK_UNIT 0x00000080
#define S3C_HSMMC_CLOCK_BASE_MASK 0x00003F00
#define S3C_HSMMC_CLOCK_BASE_SHIFT 8
#define S3C_HSMMC_MAX_BLOCK_MASK 0x00030000
#define S3C_HSMMC_MAX_BLOCK_SHIFT 16
#define S3C_HSMMC_CAN_DO_DMA 0x00400000
#define S3C_HSMMC_CAN_DO_ADMA2 0x00080000
#define S3C_HSMMC_CAN_VDD_330 0x01000000
#define S3C_HSMMC_CAN_VDD_300 0x02000000
#define S3C_HSMMC_CAN_VDD_180 0x04000000
#define S3C_HSMMC_MAXCURR (0x48)
/* For ADMA2 */
#define S3C_HSMMC_FEAER (0x50)
#define S3C_HSMMC_FEERR (0x52)
#define S3C_HSMMC_ADMAERR (0x54)
#define S3C_HSMMC_ADMAERR_CONTINUE_REQUEST (1<<9)
#define S3C_HSMMC_ADMAERR_INTRRUPT_STATUS (1<<8)
#define S3C_HSMMC_ADMAERR_LENGTH_MISMATCH (1<<2)
#define S3C_HSMMC_ADMAERR_STATE_ST_STOP (0<<0)
#define S3C_HSMMC_ADMAERR_STATE_ST_FDS (1<<0)
#define S3C_HSMMC_ADMAERR_STATE_ST_TFR (3<<0)
#define S3C_HSMMC_ADMASYSADDR (0x58)
#define S3C_HSMMC_ADMA_ATTR_MSK 0x3F
#define S3C_HSMMC_ADMA_ATTR_ACT_NOP (0<<4)
#define S3C_HSMMC_ADMA_ATTR_ACT_RSV (1<<4)
#define S3C_HSMMC_ADMA_ATTR_ACT_TRAN (2<<4)
#define S3C_HSMMC_ADMA_ATTR_ACT_LINK (3<<4)
#define S3C_HSMMC_ADMA_ATTR_INT (1<<2)
#define S3C_HSMMC_ADMA_ATTR_END (1<<1)
#define S3C_HSMMC_ADMA_ATTR_VALID (1<<0)
#define S3C_HSMMC_CONTROL2 (0x80)
#define S3C_HSMMC_CONTROL3 (0x84)
#define S3C_HSMMC_CONTROL4 (0x8C)
#define S3C_HSMMC_DEBUG (0x88)
#define S3C_HSMMC_HCVER (0xfe)
#define S3C_HSMMC_VENDOR_VER_MASK 0xFF00
#define S3C_HSMMC_VENDOR_VER_SHIFT 8
#define S3C_HSMMC_SPEC_VER_MASK 0x00FF
#define S3C_HSMMC_SPEC_VER_SHIFT 0
#endif /* __ASM_ARCH_REGS_HSMMC_H */
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