S5PV210时钟初始化

    S5PV210 包含3个时钟域：main system (MSYS), display system (DSYS), and peripheral system (PSYS).

    S5PV210 内部含有4个PLL：APLL、MPLL、EPLL、VPLL。

• Cortex A8 and MSYS clock domain uses APLL (that is, ARMCLK, HCLK_MSYS, and PCLK_MSYS). 

• DSYS and PSYS clock domain (that is, HCLK_DSYS, HCLK_PSYS, PCLK_DSYS, and PCLK_PSYS) and other peripheral clocks (that is, audio IPs, SPI, and so on) use MPLL and EPLL. 

• Video clocks uses VPLL.

    S5PV210 手册 P361 的 Figure 3-3 描述了其内部各时钟的关系。

    手册中也给出了初始化时钟的步骤：

1.Turn on a PLL (A,M,E,V)PLL_CON[31] = 1; // Power on a PLL (Refer to (A, M, E, V) PLL_CON SFR)

2.wait_lock_time; // Wait until the PLL is locked

3.(A, M, E, V)PLL_SEL = 1; // Select the PLL output clock instead of input reference clock, after PLL output clock is stabilized. (Refer to 0, 4, 8, 12th bit of CLK_SRC0 SFR) Once you turned on any PLL, do not turn off that.

4.Set PMS values; // Set PDIV, MDIV, and SDIV values (Refer to (A, M, E, V) PLL_CON SFR)

5.Change the system clock divider values

    CLK_DIV0 [31:0] = target value0;

6.Change the divider values for special clocks
    CLK_DIV1 [31:0] = target value1;
    CLK_DIV2 [31:0] = target value2;

   

    下面以一个实际的例子来说明上述的设置过程，其中寄存器的值我们多数采用手册推荐值。

    /* 目前只用到APLL和MPLL所以只设置这两个锁相环 */

    /* fin=24M fout=1000M APLL:P=3 M=125 S=1 Fref=8M */

    //turn on PLL

    APLL_CON0 = (1 << 31) | (125 << 16) | (3 << 8) | (1 << 0);

    while(!(APLL_CON0 & (1<<29)));    //wait until the PLL is locked

    //fin=24M fout=667M

    MPLL_CON = (1<<31) | (667<<16) | (12<<8) | (1<<0);
    while(!(MPLL_CON & (1<<29)));  

    CLK_SRC0 = (1<<12)|(1<<8)|(1<<4)|(1<<0);

    //ARMCLK=1000M HCLK_MSYS=200M HCLK_IMEM=100M PCLK_MSYS=100M
    //HCLK_DSYS=166M HCLK_PSYS=133M PCLK_DSYS=83M PCLK_PSYS=66.7M
    CLK_DIV0 = (0x1<<28)|(0x4<<24)|(0x1<<20)|(0x3<<16)| (1<<12) | (4<<8) | (4<<4) | (0<<0);

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