2012年（1008）
分类：
2012-08-01 10:32:17
原文地址：资料转载：VGA (VESA DDC) 作者：tekkamanninja
VGA=Video Graphics Adapter or Video Graphics Array
VESA=Video Electronics Standards Association
DDC=Display Data Channel
Contents |
Videotype: Analogue.
15 PIN HIGHDENSITY D-SUB FEMALE at the videocard.
15 PIN HIGHDENSITY D-SUB MALE at the monitor cable.
| Pin | Name | Dir | Description | Impedance/Level |
|---|---|---|---|---|
| 1 | RED |  | Red Video | 75 Ω, 0.7 V p-p |
| 2 | GREEN | | Green Video | 75 Ω, 0.7 V p-p |
| 3 | BLUE | | Blue Video | 75 Ω, 0.7 V p-p |
| 4 | RES | - | Reserved | |
| 5 | GND |  | Ground | |
| 6 | RGND | | Red Ground | |
| 7 | GGND | | Green Ground | |
| 8 | BGND | | Blue Ground | |
| 9 | +5V | | +5 VDC | |
| 10 | SGND | | Sync Ground | |
| 11 | ID0 |  | Monitor ID Bit 0 (optional) | |
| 12 | SDA |  | DDC Serial Data Line | |
| 13 | HSYNC or CSYNC | | Horizontal Sync (or Composite Sync) | |
| 14 | VSYNC | | Vertical Sync | |
| 15 | SCL | | DDC Data Clock Line |
Note: Direction is Computer relative Monitor.
VESA DPMS power savingDPMS = Device Power Management Signalling
| Signal | Power save mode | |||
|---|---|---|---|---|
| Normal | Standby | Supspended | Off | |
| 13 HSYNC | On | Off | On | Off |
| 14 VSYNC | On | On | Off | Off |
| Power level | 100% | 80% | <30W | <8W |
DDC = Display Data Channel
| Name | Pins | Protocol | |
|---|---|---|---|
| SDA | SCL | ||
| DDC1 | 12 | 14 | Unidirection protocol (uses VSYNC (14) as clock) |
| DDC2B | 15 | I2C | |
| DDC2B+ | I2C (Bidirectional) | ||
| DDC2AB | I2C (ACCESS.bus) | ||
| DDC/CI | I2C | ||
Note: DDC2 was never implemented
DDC1DDC1 is a quite simple protocol. Unidirectional communication from the monitor to the video card. VSYNC (14) is used as clock.
DDC2BBased on Philips I2C protocol. Video card is the master and monitor is always slave. Monitor has address 0xA0 (for write mode) and 0xA1 (for read mode). Control of display is not possible only exchange of information.
DDC2B+Modification to allow bidirectional communication, point to point. Both video card and monitor can be master and slave. Control of display is possible.
DDC2AB/DDC2B+Monitors that implement DDC2AB/DDC2B+ are full featured ACCESS.bus devices. Multiple devices on one bus. ACCESS.bus is based on Philips I2C protocol. Default address for monitor is 0x6e and 0x50 for video card (host). Extra information is transmitted thru VDIF (VESA Video Display Information Format).
DDC/CI (formerly DDC2Bi)DDC/CI = Display Data Channel Command Interface E-DDC (VESA Enhanced Extended Display Data Channel Standard) is the physical standard.
Extended Display Identification DataEDID = Extended Display Identification Data
EDID 1.0/1.1The EDID information consists of 128 bytes of monitor data.
Additional blocks of 128 bytes can be stored in EDID extension blocks (aka VDIF) after the initial EDID block. These blocks contain addtional detailed timing information. There is a flag within the EDID to indicate the existence of these blocks. VDIF is not currently used in our systems.
| Version | Revision | Year | Standard |
|---|---|---|---|
| 1 | 0 | 1994 | DDC |
| 1 | 1 | 1996 | EDID Standard v2 |
| 1 | 2 | 1997 | EDID Standard v3 |
| 2 | 0 | 1997 | EDID Standard v3 (Discouraged for future designs) |
| 1 | 3 | 1999 | E-EDID Rel A |
| Offset | Name | Description | |
|---|---|---|---|
| 00h-07h | Header | 00h, FFh, FFh, FFh, FFh, FFh, FFh, 00h | |
| 08h-09h | Vendor/Product ID | Manufacturer ID | provided by Microsoft |
| 0Ah-0Bh | Product ID | assigned by manufacturer | |
| 0Ch-0Fh | Serial number | ||
| 10h | Manufacturing date | Week | 1-54 |
| 11h | Year | Year-1990 (must be >3) | |
| 12h | EDID verion | Version | Current version 1 |
| 13h | Revision | Current revision 3 | |
| 14h | Basic Display Parameters | Video Input Definition |
|
| 15h | Width | in cm, 0 for projectors | |
| 16h | Height | in cm, 0 for projectors | |
| 17h | Gamma | ||
| 18h | Power Management support |
| |
Note: Little-endian
E-EDIDE-EDID = Enhanced Extended Display Identification Data Standard Up to 32kB of data.
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