u-boot-1.3.2移植记录（二）

文件夹，开始配置44B0电路板。

A.        修改lowlevel_init.S。lowlevel_init.S是有关外部设备的读写时序、延时的配置文件，可以用LIYUTAI的配置就可以了。（LIYUTAI的RAM配置不是太好，但是还能勉强用上，只是慢一点点而已。）

.equ    B0_Tacs,      0x0 /* 0clk */

.equ    B0_Tcos,      0x1 /* 0clk */

.equ    B0_Tacc,      0x6 /* 10clk */

.equ    B0_Tcoh,      0x1 /* 0clk */

.equ    B0_Tah,       0x0 /* 0clk */

.equ    B0_Tacp,      0x0 /* 0clk */

.equ    B0_PMC,       0x0 /* normal(1data) */

/* Bank 1 parameter */

.equ    B1_Tacs,      0x3 /* 4clk */

.equ    B1_Tcos,      0x3 /* 4clk */

.equ    B1_Tacc,      0x7 /* 14clkv */

.equ    B1_Tcoh,      0x3 /* 4clk */

.equ    B1_Tah,       0x3 /* 4clk */

.equ    B1_Tacp,      0x3 /* 6clk */

.equ    B1_PMC,       0x0 /* normal(1data) */

 

/* Bank 2 parameter */

.equ    B2_Tacs,      0x3 /* 4clk */

.equ    B2_Tcos,      0x3 /* 4clk */

.equ    B2_Tacc,      0x7 /* 14clk */

.equ    B2_Tcoh,      0x3 /* 4clk */

.equ    B2_Tah,       0x3 /* 4clk */

.equ    B2_Tacp,      0x3 /* 6clk */

.equ    B2_PMC,       0x0 /* normal(1data) */

 

/* Bank 3 parameter */

.equ    B3_Tacs,      0x3 /* 4clk */

.equ    B3_Tcos,      0x3 /* 4clk */

.equ    B3_Tacc,      0x7 /* 14clk */

.equ    B3_Tcoh,      0x3 /* 4clk */

.equ    B3_Tah,       0x3 /* 4clk */

.equ    B3_Tacp,      0x3 /* 6clk */

.equ    B3_PMC,       0x0 /* normal(1data) */

 

/* Bank 4 parameter */

.equ    B4_Tacs,      0x3 /* 4clk */

.equ    B4_Tcos,      0x3 /* 4clk */

.equ    B4_Tacc,      0x7 /* 14clk */

.equ    B4_Tcoh,      0x3 /* 4clk */

.equ    B4_Tah,       0x3 /* 4clk */

.equ    B4_Tacp,      0x3 /* 6clk */

.equ    B4_PMC,       0x0 /* normal(1data) */

 

/* Bank 5 parameter */

.equ    B5_Tacs,      0x3 /* 4clk */

.equ    B5_Tcos,      0x3 /* 4clk */

.equ    B5_Tacc,      0x7 /* 14clk */

.equ    B5_Tcoh,      0x3 /* 4clk */

.equ    B5_Tah,       0x3 /* 4clk */

.equ    B5_Tacp,      0x3 /* 6clk */

.equ    B5_PMC,       0x0 /* normal(1data) */

 

/* Bank 6(if SROM) parameter */

.equ    B6_Tacs,      0x3 /* 4clk */

.equ    B6_Tcos,      0x3 /* 4clk */

.equ    B6_Tacc,      0x7 /* 14clk */

.equ    B6_Tcoh,      0x3 /* 4clk */

.equ    B6_Tah,       0x3 /* 4clk */

.equ    B6_Tacp,      0x3 /* 6clk */

.equ    B6_PMC,       0x0 /* normal(1data) */

 

/* Bank 7(if SROM) parameter */

.equ    B7_Tacs,      0x3 /* 4clk */

.equ    B7_Tcos,      0x3 /* 4clk */

.equ    B7_Tacc,      0x7 /* 14clk */

.equ    B7_Tcoh,      0x3 /* 4clk */

.equ    B7_Tah,       0x3 /* 4clk */

.equ    B7_Tacp,      0x3 /* 6clk */

.equ    B7_PMC,       0x0 /* normal(1data) */

 

/* Bank 6 parameter */

.equ    B6_MT,        0x3 /* SDRAM */

.equ    B6_Trcd,      0x1 /* 2clk */

.equ    B6_SCAN,      0x0 /* 10bit */

 

.equ    B7_MT,        0x3 /* SDRAM */

.equ    B7_Trcd,      0x1 /* 2clk */

.equ    B7_SCAN,      0x0 /* 10bit */

 

 

/* REFRESH parameter */

.equ    REFEN,                 0x1 /* Refresh enable */

.equ    TREFMD,                     0x0 /* CBR(CAS before RAS)/Auto refresh */

.equ    Trp,                0x1 /* 2clk */

.equ    Trc,                0x1 /* 0x1=5clk 0x3=11clk*/

.equ    Tchr,               0x2 /* 0x2=3clk 0x0=0clks  */

.equ    REFCNT,               1050 //;period=15.6us, MCLK=64Mhz

 

MEMORY_CONFIG:

  .long   0x11010101 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/

  .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/

  .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/

  .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/

  .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/

  .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/

  .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/

  .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  /*GCS6*/

  .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  /*GCS7*/

  .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/

  .word 0x17      /*SCLK power down mode, BANKSIZE 16M/16M*/

  .word 0x20      /*MRSR6 CL=2clk*/

  .word 0x20      /*MRSR7*/

 

B.        修改44B0.c文件里面的board_init函数，这个函数是U-BOOT完成底层初始化之后进入的第一个C函数。

int board_init (void)

{

       //CAUTION:Follow the configuration order for setting the ports.

       // 1) setting value

        // 2) setting control register

        // 3) configure pull-up resistor.

 

       //16bit data bus configuration

 

       // PORT A GROUP

       /*  BIT    9 8     7     6     5     4     3     2     1     0     */

       /*        A24      A23 A22 A21 A20 A19 A18 A17 A16 A0   */

       /*        1          1     1     1     1     1     1     1     1     1     */

       PCONA = 0x3ff;

 

       // PORT B GROUP

       /*  BIT 10     9            8            7            6            5            4            3            2            1            0            */

       /*    /CS5       /CS4       /CS3       /CS2       /CS1       nWBE3   nWBE2   /SRAS     /SCAS     SCLK      SCKE      */

       /*    EXT              NIC        USB        IDE        SMC              NC         NC         Sdram     Sdram     Sdram       Sdram     */

       /*      1,        1,   1,   1,    1,    1,       1,     1,    1,    1,   1          */

       PDATB = 0x7ff;

       PCONB = 0x7cf;

 

       //PORT C GROUP

       //BUSWIDTH=16                                                                                       */

       /*  PC15       14           13           12           11           10           9            8     */

       /*    I             O            RXD1     TXD1     I             I             I             I      */

       /* PS2DAT     DCLK     Uart1      Uart1      NC         NC         NC         NC  */

       /*   00          01           11           11           00           00           00           00    */

 

       /*  PC7         6            5            4            3            2            1            0     */

       /*   I            I             I             I             I             I             I             I      */

       /*   VD4       VD5        VD6        VD7        SMCALE SMCCLE SMCCE   SMCRB*/

       /*   00          00           00           00           01           01           01           00    */

       PDATC = 0xffff;    //All IO is high

       PCONC = 0x1f05ff54;

       PUPC  = 0x3000;  //PULL UP RESISTOR should be enabled to I/O

 

       //PORT D GROUP

       /*  PORT D GROUP(I/O OR LCD)                                                                   */

       /*  BIT  7            6            5            4            3            2            1            0     */

       /*  VF          VM         VLINE    VCLK     VD3        VD2        VD1        VD0 */

       /*       00            00           00           00           00           00           00           00    */

       PDATD= 0xff;

       PCOND= 0xaaaa;

       PUPD = 0x0;

       //These pins must be set only after CPU's internal LCD controller is enable

 

       //PORT E GROUP

       /*  Bit 8 7     6     5     4     3     2     1     0     */

       /*      LcdBL     LED4      LED5      LED6      LED7      BEEP      RXD0     TXD0     LcdDisp  */

       /*      01    01    01    01    01    01    10    10    01    */

       PDATE    = 0x1ff;

       PCONE   = 0x25569;

       PUPE      = 0x6;

 

       //PORT F GROUP

       /*  Bit8         7            6            5            4           3            2            1            0            */

       /*  IISCLK    IISDI      IISDO     IISLRCK Input       Input       Input       IICSDA   IICSCL   */

       /*    100         100         100         100         00           00           00           10           10           */

       PDATF = 0x0;

       PCONF = 0x24900a;

       PUPF  = 0x1e3;

 

       //PORT G GROUP

       /*  BIT7        6            5            4            3            2            1            0     */

       /*    INT7             INT6             INT5             INT4             INT3             INT2             INT1             INT0       */

       /*    S3        S4          S5          S6          NIC        EXT              IDE        USB */

       /*      11      11      11      11      11      11      11      11       */

       //rPDATG = 0xff;

       //rPCONG = 0xffff;

       PCONG = 0x00ff; //EXINT0~3 enabled

       PUPG  = 0x0;       //pull-up regiseter should be enabled

 

       SPUCR=0x7;  //D15-D0 pull-up disable

 

       /*均为低电平触发,Exint3设置为上升沿触发----modify at 04-12-11*/

       EXTINT=0x0|(1<<14);

 

       return 0;

}

可以直接使用LIYUTAI的端口初始化函数来代替就可以了。

 

C.        修改Makefile文件，把B2.o替换为44B0.o

 

D.       修改config.mk文件，把TEXT_BASE的值改成0x0C300000。这个只是为了预留2M的空间来下载内核。U-BOOT启动时会把代码拷贝到TEXT_BASE的位置上，如果不修改这个值，下载大一点的代码就会死机的。

 

E.        修改board/armsys/common/flash.c的配置，增加flash支持。

flash.c:

       case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:

case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601:

                            并替换所有B2为44B0，这样才能在编译的时候编译进去

 

至此，44B0的电路板已经配置完成。接着就修改配置文件。

 

文件。

以下是我的整个44B0.h配置文件

#ifndef __CONFIG_H

#define __CONFIG_H

 

/*

 * High Level Configuration Options

 * (easy to change)

 */

#define CONFIG_ARM7                     1     /* This is a ARM7 CPU  */

#define CONFIG_44B0                1     /* on an 44B0 Board      */

#define CONFIG_ARM_THUMB  1     /* this is an ARM7TDMI */

#undef  CONFIG_ARM7_REVD      /* disable ARM720 REV.D Workarounds */

 

#define CONFIG_S3C44B0_CLOCK_SPEED      64 /* we have a 75Mhz S3C44B0*/

 

//#define CONFIG_MEM_TEST                 //do ram test

 

#define CONFIG_SILENT_CONSOLE        1     //config with silent

 

#undef CONFIG_USE_IRQ                 /* don't need them anymore */

 

 

/*

 * Size of malloc() pool

 */

#define CFG_MONITOR_LEN            (256 * 1024)   /* Reserve 256 kB for Monitor      */

#define CFG_ENV_SIZE              1024              /* 1024 bytes may be used for env vars*/

#define CFG_MALLOC_LEN              (CFG_ENV_SIZE + 128*1024 )

#define CFG_GBL_DATA_SIZE    128  /* size in bytes reserved for initial data */

 

/*

 * Hardware drivers

 */

//#define CONFIG_DRIVER_LAN91C96

//#define CONFIG_LAN91C96_BASE         0x04000300 /* base address         */

//#define CONFIG_SMC_USE_32_BIT

//#undef  CONFIG_SHOW_ACTIVITY

//#define CONFIG_NET_RETRY_COUNT         10       /* # of retries          */

#define CONFIG_DRIVER_RTL8019

#define RTL8019_BASE        0x08000000

//#define ET_DEBUG                   //DEBUG the ethernet

 

/*

 * select serial console configuration

 */

#define CONFIG_SERIAL1          1     /* we use Serial line 1 */

 

/* allow to overwrite serial and ethaddr */

#define CONFIG_ENV_OVERWRITE

 

#define CONFIG_BAUDRATE             115200

 

/*

 * BOOTP options

 */

#define CONFIG_BOOTP_SUBNETMASK

#define CONFIG_BOOTP_GATEWAY

#define CONFIG_BOOTP_HOSTNAME

#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_BOOTP_BOOTFILESIZE

 

/*

 * Command line configuration.

 */

#include

 

#define CONFIG_CMD_DATE

#define CONFIG_CMD_ELF

//#define CONFIG_CMD_EEPROM

//#define CONFIG_CMD_I2C

#define CONFIG_CMD_PING                   //ping cmd enable

#define CONFIG_CMD_FLASH          //nor flash support

//#define CONFIG_CMD_NAND                //nand flash support

 

 

#define CONFIG_BOOTDELAY   1

#define CONFIG_ETHADDR       00:50:c2:1e:af:fb

#define CONFIG_BOOTARGS  "setenv bootargs root=/dev/ram ip=192.168.1000.70:::::eth0:off \

       ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"

#define CONFIG_NETMASK  255.255.255.0

#define CONFIG_IPADDR   192.168.100.70

#define CONFIG_SERVERIP       192.168.100.163

#define CONFIG_BOOTFILE       "image.ram"

//#define CONFIG_BOOTCOMMAND "bootm 20000 f0000"

//#define CONFIG_BOOTCOMMAND "base 0"          //for debuging

#define CONFIG_BOOTCOMMAND   "?"          //for debuging

 

/*

 * Miscellaneous configurable options

 */

#define    CFG_LONGHELP                       /* undef to save memory              */

#define    CFG_PROMPT             "U-Boot(Ken Wu)>  "   /* Monitor Command Prompt       */

#define    CFG_CBSIZE        256         /* Console I/O Buffer Size     */

#define    CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

#define    CFG_MAXARGS          16           /* max number of command args  */

#define CFG_BARGSIZE             CFG_CBSIZE /* Boot Argument Buffer Size       */

 

#define CFG_MEMTEST_START 0x0C400000   /* memtest works on     */

#define CFG_MEMTEST_END           0x0C800000   /* 4 ... 8 MB in DRAM  */

 

#undef  CFG_CLKS_IN_HZ              /* everything, incl board info, in Hz */

 

#define    CFG_LOAD_ADDR             0x0c008000    /* default load address   */

 

#define    CFG_HZ                      1000              /* 1 kHz */

 

                                          /* valid baudrates */

#define CFG_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }

 

/*-----------------------------------------------------------------------

 * Stack sizes

 *

 * The stack sizes are set up in start.S using the settings below

 */

#define CONFIG_STACKSIZE     (128*1024)     /* regular stack */

#ifdef CONFIG_USE_IRQ

#define CONFIG_STACKSIZE_IRQ    (4*1024) /* IRQ stack */

#define CONFIG_STACKSIZE_FIQ     (4*1024) /* FIQ stack */

#endif

 

/*-----------------------------------------------------------------------

 * Physical Memory Map

 */

#define CONFIG_NR_DRAM_BANKS 1        /* we have 1 banks of DRAM */

#define PHYS_SDRAM_1            0x0C000000 /* SDRAM Bank #1 */

#define PHYS_SDRAM_1_SIZE   0x00800000 /* 8 MB */

 

//#define CONFIG_HAS_DATAFLASH               //we have flash

#define PHYS_FLASH_1              0x00000000 /* Flash Bank #1 */

#define PHYS_FLASH_SIZE        0x00200000 /* 2 MB */

 

//#define CFG_FLASH_BASE              PHYS_FLASH_1

 

/*-----------------------------------------------------------------------

 * FLASH and environment organization

 */

/*-----------------------------------------------------------------------

 * FLASH organization

 */

#define CFG_MAX_FLASH_BANKS    1     /* max number of memory banks         */

#define CFG_MAX_FLASH_SECT      32    /* max number of sectors on one chip  */

#define FLASH_BLOCK_SIZE      0x00010000   //flash的block大小

 

#define CFG_FLASH_ERASE_TOUT   120000    /* Timeout for Flash Erase (in ms)       */

#define CFG_FLASH_WRITE_TOUT  1000       /* Timeout for Flash Write (in ms)       */

 

#define CFG_FLASH_WORD_SIZE     unsigned short       /* flash word size (width)     */

#define CFG_FLASH_ADDR0             0x5555    /* 1st address for flash config cycles   */

#define CFG_FLASH_ADDR1             0x2AAA  /* 2nd address for flash config cycles  */

/*

 * The following defines are added for buggy IOP480 byte interface.

 * All other boards should use the standard values (CPCI405 etc.)

 */

#define CFG_FLASH_READ0             0x0000    /* 0 is standard                    */

#define CFG_FLASH_READ1             0x0001    /* 1 is standard                    */

#define CFG_FLASH_READ2             0x0002    /* 2 is standard                    */

 

#define CFG_FLASH_EMPTY_INFO          /* print 'E' for empty sector on flinfo */

 

/**

 * NAND flash organization & operation

 */

#if defined(CONFIG_CMD_NAND)

 

#define NAND_DEBUG               1                   //debug the nand info

#define CFG_NAND_LEGACY

#define CFG_NAND_BASE          0x02000000

#define CFG_MAX_NAND_DEVICE   1     /* Max number of NAND devices        */

#define SECTORSIZE 512

 

#define ADDR_COLUMN            1

#define ADDR_PAGE                  2

#define ADDR_COLUMN_PAGE        3

 

#define NAND_ChipID_UNKNOWN   0x00

#define NAND_MAX_FLOORS   1

#define NAND_MAX_CHIPS             1

 

#define NAND_WAIT_READY(nand)   WAIT_RB()

 

#define NAND_DISABLE_CE(nand)    ST_INVALID()

#define NAND_ENABLE_CE(nand)

 

 

#define WRITE_NAND_COMMAND(d, adr)      NAND_write_cmd(d)

//#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)

#define WRITE_NAND_ADDRESS(d, adr) NAND_write_addr(d)

#define WRITE_NAND(d, adr)                   NAND_write(d)

#define READ_NAND(adr)                        NAND_read()

/*

 * the following functions are NOP's because S3C24X0 handles this in hardware

 * but it must define in S344B0 board because the board does not support the interface

 */

#define NAND_CTL_CLRALE(nandptr)

#define NAND_CTL_SETALE(nandptr)

#define NAND_CTL_CLRCLE(nandptr)

#define NAND_CTL_SETCLE(nandptr)

 

//do not use write verify and jffs2 ecc at first

//#define CONFIG_MTD_NAND_VERIFY_WRITE   1

//#define CONFIG_MTD_NAND_ECC_JFFS2    1

 

#endif

 

/*-----------------------------------------------------------------------

 * Environment Variable setup

 */

//#define CFG_ENV_IS_IN_EEPROM  1     /* use EEPROM for environment vars */

//#define CFG_ENV_OFFSET             0x0  /* environment starts at the beginning of the EEPROM */

#define CFG_ENV_IS_IN_FLASH              1

#undef CFG_ENV_IS_NOWHERE

#define CFG_FLASH_BASE                PHYS_FLASH_1

#define CFG_ENV_OFFSET               0x100000       //从0x10000处开始保存系统参数

//#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x20000) /* environment start address */

#define CFG_ENV_SECT_SIZE       0x10000              /* Total Size of Environment Sector */

//#define CFG_MONITOR_BASE PHYS_SDRAM_1

 

/*-----------------------------------------------------------------------

 * I2C EEPROM (STM24C02W6) for environment

 */

//#define CONFIG_HARD_I2C                   /* I2c with hardware support */

//#define CFG_I2C_SPEED          400000    /* I2C speed and slave address */

//#define CFG_I2C_SLAVE          0xFE

//

//#define CFG_I2C_EEPROM_ADDR  0xA8       /* EEPROM STM24C02W6         */

//#define CFG_I2C_EEPROM_ADDR_LEN 1     /* Bytes of address        */

///* mask of address bits that overflow into the "EEPROM chip address"   */

///*#define CFG_I2C_EEPROM_ADDR_OVERFLOW       0x07*/

//#define CFG_EEPROM_PAGE_WRITE_BITS 4       /* The Catalyst CAT24WC08 has  */

                                   /* 16 byte page write mode using*/

                                   /* last 4 bits of the address    */

//#define CFG_EEPROM_PAGE_WRITE_DELAY_MS      10   /* and takes up to 10 msec */

//#define CFG_EEPROM_PAGE_WRITE_ENABLE

 

/* Flash banks JFFS2 should use */

/*

#define CFG_JFFS2_FIRST_BANK    0

#define CFG_JFFS2_FIRST_SECTOR 2

#define CFG_JFFS2_NUM_BANKS     1

*/

 

/*

       Linux TAGs (see lib_arm/armlinux.c)

*/

#define CONFIG_CMDLINE_TAG

#undef CONFIG_SETUP_MEMORY_TAGS

#define CONFIG_INITRD_TAG

 

#endif     /* __CONFIG_H */

 

至此，配置已经完成，可以make出镜像来了！！J

 

镜像

make 44B0_config

make CROSS_COMPILE=arm-linux-

（一大堆编译信息飘过。。。）

最后，你就可以看到u-boot.bin镜像文件了。烧进flash里面就可以直接运行了！^_^