摘自 arm architecture reference manual.
B2.2.4 Cache maintenance functionality
ARMv7 redefines the required CP15 cache maintenance operations. The two main features of this change
are:
? improved support for multiple levels of cache, including abstracting how many levels of cache are
implemented.
? reducing the architecturally-defined set of operations to the minimum set required for operating
systems
This section only describes cache maintenance for ARMv7. For details of cache maintenance in previous
versions of the ARM architecture see:
? c7, Cache operations on page AppxG-38 for ARMv6
? c7, Cache operations on page AppxH-49 for the ARMv4 and ARMv5 architectures.
Terms used in describing cache operations on page B2-10 describes the terms used in this section. Then the
following subsections describe the ARMv7 cache maintenance functionality:
? ARMv7 cache maintenance operations on page B2-13
? The ARMv7 abstraction of the cache hierarchy on page B2-15.
Terms used in describing cache operations
This section describes particular terms used in the descriptions of cache maintenance operations.
Cache maintenance operations are defined to act on particular memory locations. Operations can be defined:
? by the address of the memory location to be maintained, referred to as by MVA
? by a mechanism that describes the location in the hardware of the cache, referred to as by set/way.
In addition, the instruction cache invalidate operation has an option that invalidates all entries in the
instruction caches.
The following subsections define the terms used to describe the cache operations:
? Operations by MVA
? Operations by set/way
? Clean, Invalidate, and Clean and Invalidate on page B2-11.
Operations by MVA
For cache operations by MVA, these terms relate to memory addressing, and in particular the relation
between:
? Modified Virtual Address (MVA)
? Virtual Address (VA)
? Physical Address (PA).
The term Modified Virtual Address relates to the Fast Context Switch Extension (FCSE) mechanism,
described in Appendix E Fast Context Switch Extension (FCSE). Use of the FCSE is deprecated in ARMv6
and the FCSE is optional in ARMv7. When the FCSE is absent or disabled, the MVA and VA have the same
value. However the term MVA is used throughout this section, and elsewhere in this manual, for cache and
TLB operations. This is consistent with previous issues of the ARM Architecture Reference Manual.
Virtual addresses only exist in systems with a MMU. When no MMU is implemented or the MMU is
disabled, the MVA and VA are identical to the PA.
In the cache operations, any operation described as operating by MVA includes as part of any required MVA
to PA translation:
? the current system Application Space IDentifier (ASID)
? the current security state, if the Security Extensions are implemented.
Operations by set/way
Cache maintenance operations by set/way refer to the particular structures in a cache. Three parameters
describe the location in a cache hierarchy that an operation works on. These parameters are:
Level The cache level of the hierarchy. The number of levels of cache is IMPLEMENTATION
DEFINED, and can be determined from the Cache Level ID Register, see:
? c0, Cache Level ID Register (CLIDR) on page B3-92 for a VMSA implementation
? c0, Cache Level ID Register (CLIDR) on page B4-41 for a PMSA implementation.
In the ARM architecture, the lower numbered levels are those closest to the processor, see
Memory hierarchy on page A3-52.
Set Each level of a cache is split up into a number of sets. Each set is a set of locations in a cache
level that an address can be assigned to. Usually, the set number is an IMPLEMENTATION
DEFINED function of an address.
In the ARM architecture, sets are numbered from 0.
Way The Associativity of a cache defines the number of locations in a set that an address can be
assigned to. The way number specifies a location in a set. In the ARM architecture, ways are
numbered from 0.
Cache maintenance operations that work by set/way use the level, set and way values to determine the
location acted on by the operation. The address in memory that corresponds to this cache location is
determined by the cache.
Note
Because the allocation of a memory address to a cache location is entirely IMPLEMENTATION DEFINED, ARM
expects that most portable code will use only the set/way operations as single steps in a routine to perform
maintenance on the entire cache.
Clean, Invalidate, and Clean and Invalidate
Caches introduce coherency problems in two possible directions:
1. An update to a memory location by a processor that accesses a cache might not be visible to other
observers that can access memory. This can occur because new updates are still in the cache and are
not visible yet to the other observers that do not access that cache.
2. Updates to memory locations by other observers that can access memory might not be visible to a
processor that accesses a cache. This can occur when the cache contains an old, or stale, copy of the
memory location that has been updated.
The Clean and Invalidate operations address these two issues. The definitions of these operations are:
Clean A cache clean operation ensures that updates made by an observer that controls the cache
are made visible to other observers that can access memory at the point to which the
operation is performed. Once the Clean has completed, the new memory values are
guaranteed to be visible to the point to which the operation is performed, for example to the
point of unification.
The cleaning of a cache entry from a cache can overwrite memory that has been written by
another observer only if the entry contains a location that has been written to by a processor
that controls that cache.
Invalidate A cache invalidate operation ensures that updates made visible by observers that access
memory at the point to which the invalidate is defined are made visible to an observer that
controls the cache. This might result in the loss of updates to the locations affected by the
invalidate operation that have been written by observers that access the cache.
If the address of an entry on which the invalidate operates does not have a Normal Cacheable
attribute, or if the cache is disabled, then an invalidate operation also ensures that this
address is not present in the cache.
Note
Entries for addresses with a Normal Cacheable attribute can be allocated to an enabled cache
at any time, and so the cache invalidate operation cannot ensure that the address is not
present in the cache.
Clean and Invalidate
A cache clean and invalidate operation behaves as the execution of a clean operation
followed immediately by an invalidate operation. Both operations are performed to the same
location.
The points to which a cache maintenance operation can be defined differ depending on whether the
operation is by MVA or by set/way:
? For set/way operations, and for All (entire cache) operations, the point is defined to be to the next
level of caching.
? For MVA operations, two conceptual points are defined:
Point of coherency (POC)
For a particular MVA, the POC is the point at which all agents that can access memory
are guaranteed to see the same copy of a memory location. In many cases, this is
effectively the main system memory, although the architecture does not prohibit the
implementation of caches beyond the POC that have no effect on the coherence between
memory system agents.
Point of unification (POU)
The PoU for a processor is the point by which the instruction and data caches and the
translation table walks of that processor are guaranteed to see the same copy of a memory
location. In many cases, the point of unification is the point in a uniprocessor memory
system by which the instruction and data caches and the translation table walks have
merged.
The PoU for an Inner Shareable shareability domain is the point by which the instruction
and data caches and the translation table walks of all the processors in that Inner
Shareable shareability domain are guaranteed to see the same copy of a memory location.
Defining this point permits self-modifying code to ensure future instruction fetches are
associated with the modified version of the code by using the standard correctness policy
of:
1. clean data cache entry by address
2. invalidate instruction cache entry by address.
The PoU also enables a uniprocessor system which does not implement the
Multiprocessing Extensions to use the clean data cache entry operation to ensure that all
writes to the translation tables are visible to the translation table walk hardware.
Three field definitions in the Cache Level ID Register relate to these conceptual points:
Level of Coherence
The level of coherence field defines the first level of cache that does not have to be
cleaned or invalidated when cleaning or invalidating to the point of coherency. The value
in the register is one less than the cache level, so a value of 0 indicates level 1 cache. For
example, if the level of coherence field contains the value 3:
? level 4 cache is the first level that does not have to be cleaned or invalidated
? therefore, a clean to the point of coherency operation requires the level 1, level 2
and level 3 caches to be cleaned.
The specified level of coherence can be a level that is not implemented, indicating that all
implemented caches are before the point of coherency.
Level of Unification Uniprocessor
The Level of Unification Uniprocessor field defines the first level of cache that does not
have to be cleaned or invalidated when cleaning or invalidating to the point of unification
for the processor. As with the Level of Coherence, the value in the register is one less than
the cache level, so a value of 0 indicates Level 1 cache.
The specified Level of Unification Uniprocessor can be a level that is not implemented,
indicating that all implemented caches are before the point of unification.
Level of Unification Inner Shareable
The Level of Unification Inner Shareable field defines the first level of cache that does
not have to be cleaned or invalidated when cleaning or invalidating to the point of
unification for the Inner Shareable shareability domain. As with the Level of Coherence,
the value in the register is one less than the cache level, that means a value of 0 indicates
Level 1 cache.
The specified Level of Unification Inner Shareable can be a level that is not implemented,
indicating that all implemented caches are before the point of unification.
The Level of Unification Inner Shareable field is RAZ in implementations that do not
implement the Multiprocessing Extensions.
For more information, see:
— c0, Cache Level ID Register (CLIDR) on page B3-92 for a VMSA implementation
— c0, Cache Level ID Register (CLIDR) on page B4-41 for a PMSA implementation.
ARMv7 cache maintenance operations
Cache maintenance operations are performed using accesses to CP15 c7. The operations are described in:
? CP15 c7, Cache and branch predictor maintenance functions on page B3-126, for a VMSA
implementation
? CP15 c7, Cache and branch predictor maintenance functions on page B4-68, for a PMSA
implementation.
Common Memory System Architecture Features
B2-14 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
This operations required by ARMv7 are:
Data cache and unified cache line operations
Any of these operations can be applied to
? any data cache
? any unified cache.
The supported operations are:
Invalidate by MVA
Performs an invalidate of a data or unified cache line based on the address it
contains.
Invalidate by set/way
Performs an invalidate of a data or unified cache line based on its location in the
cache hierarchy.
Clean by MVA
Performs a clean of a data or unified cache line based on the address it contains.
Clean by set/way
Performs a clean of a data or unified cache line based on its location in the cache
hierarchy.
Clean and Invalidate by MVA
Performs a clean and invalidate of a data or unified cache line based on the
address it contains.
Clean and Invalidate by set/way
Performs a clean and invalidate of a data or unified cache line based on its
location in the cache hierarchy.
Instruction cache operations
Invalidate by MVA
Performs an invalidate of an instruction cache line based on the address it
contains.
Invalidate All
Performs an invalidate of the entire instruction cache or caches, and of all
Branch Prediction caches.
Note
Other cache maintenance operations specified in ARMv6 are not supported in ARMv7. Their associated
encodings in CP15 c7 are UNPREDICTABLE.
