s3c2440寄存器

ARM9(S3C2440)的13个存储控制寄存器

2009-04-29 21:45

内存控制器地址，摘自三星技术手册：

BWSCON   0x48000000           R/W Bus Width & Wait Status Control
BANKCON0 0x48000004         Boot ROM Control
BANKCON1 0x48000008         BANK1 Control
BANKCON2 0x4800000C         BANK2 Control
BANKCON3 0x48000010         BANK3 Control
BANKCON4 0x48000014         BANK4 Control
BANKCON5 0x48000018         BANK5 Control
BANKCON6 0x4800001C         BANK6 Control
BANKCON7 0x48000020         BANK7 Control
REFRESH 0x48000024           DRAM/SDRAM Refresh Control
BANKSIZE 0x48000028           Flexible Bank Size
MRSRB6   0x4800002C           Mode register set for SDRAM BANK6
MRSRB7   0x48000030           Mode register set for SDRAM BANK7

BWSCON，共32位:

31~28：BANK7
27~24：BANK6
。。。。。
3～0：BANK0

BANK7～BANK1设置一致

四位分别代表：
STx：和树上说的不一样，手册说表示 SRAM for using UB/LB ，0不使用，1使用，一般接0
WSx ：是否插入等待信号，0否，1是，一般选0
DWx（2位）：00 8位，01 16位，10 32位，11 保留。这个每一个BANK可以根据书上 P91页表格看BANK的宽度。

BANK0比较特殊，
3：保留，写0
2～1（只读）：取00，由硬件决定，因为你写不进去东西。。
0：保留，取0
总之BANK0就是0000（2进制）就对了

由此就得来了，这块板子上，0x22011110

BANKCON0～5（对应BANK 0～5，每个寄存器32位）：保留值，写入0x00000700即可。

BANKCON6～7（对应BANK 6～7，每个寄存器32位）：

31～17位，设为0

16~15，11表示BANKx接了SDRAM,00 SRAM，我的开发板BANK6接的是SRAM当然是11了

如果是SRAM就按照上面的000700就好了，如果是SDRAM，只需要设置3～0

3～2：CAS用几个周期，推荐为3个周期，01
1～0：列信号有几根线。。
mini2440的SDRAM芯片是HY57V561620（L）T，
光盘里的pdf手册显示了如下内容：Column Address : CA0 ~ CA8，因此是9根，所以取01
综上，BANKCON6~7的取值为 0x00018005

REFRESH（32位，用于设定SDRAM的刷新）：

23：是否开启SDRAM刷新，自然选1开启
22：SDRAM刷新模式，选0
21～20：取00或者10，RAS的change时间
19～18：行时间，取11
17～11：0

10~0：就是刷新频率了～～

计算公式，R_CNT=2^11+1-SDRAM时钟频率（Mhz）＊SDRAM刷新周期（uS）

HY那个手册上写到：8192个刷新周期用64ms，因此刷新周期＝64000/8192=7.8125
时钟频率有好多种啊，先实验为100Mhz的吧。。

因此计算出来就是1267.75，四舍五入1268－>0x04f4

因此这个REFRESH取值是 0x008c04f4，简单计算方法就是0x008c0000 + 04f4

BANKSIZE（32为寄存器）：

支持核突发，使用SCKE，仅在SDRAM期间发出SCLK，地址空间64Mb
因此BANKSIZE为 0x000000B1

MRSRB6~7（SDRAM模式设置）

3个时钟周期，0x30

The S3C2410X has 117 multi-functional input/output port pins. The ports are:
— Port A (GPA): 23-output port
— Port B (GPB): 11-input/output port
— Port C (GPC): 16-input/output port
— Port D (GPD): 16-input/output port
— Port E (GPE): 16-input/output port
— Port F (GPF): 8-input/output port
— Port G (GPG): 16-input/output port
— Port H (GPH): 11-input/output port

---PORT A 23-output

GPACON 0x56000000
GPADAT 0x56000004

---PORT B 11-input/output

GPBCON 0x56000010
GPBDAT 0x56000014
GPBUP 0x56000018

---PORT C 16-input/output

GPCCON 0x56000020
GPCDAT 0x56000024
GPCUP 0x56000028

---PORT D 16-input/output

GPDCON 0x56000030
GPDDAT 0x56000034
GPDUP 0x56000038

---PORT E 16-input/output

GPECON 0x56000040
GPEDAT 0x56000044
GPEUP 0x56000048

---PORT F 8-input/output

GPFCON 0x56000050
GPFDAT 0x56000054
GPFUP 0x56000058

---PORT G 16-input/output

GPGCON 0x56000060
GPGDAT 0x56000064
GPGUP 0x56000068

---PORT H 11-input/output

GPHCON 0x56000070
GPHDAT 0x56000074
GPHUP 0x56000078

 

 

NAND 寄存器

2009-05-24 13:02

NFCONF 0x4E000000 R/W NAND Flash configuration

[15]       Enable/Disable   After auto-boot, this bit is cleared to 0 automatically.
                                       For the access to the NAND flash memoty, this bit must be set.
[14:13] Reserbed
[12]         Initialize ECC
[11]        NAND Flash Memory chip enable 0:nFCE=L(active), 1:nFCE=H
[10:8]     TACLS
[7]
[6:4]        TWRPH0
[3]
[2:0]        TWRPH1

NFCMD 0x4E000004 R/W NAND flash command set register
[7:0]   CMD NAND Flash memory command value

NFADDR 0x4E000008 R/W NAND flash address set register
[7:0]   Address NAND flash memory address value

NFDATA 0x4E00000C R/W NAND flash data register
[7:0]   Data       Nand flsh read/program data value

NFSTAT 0x4E000010 R NAND Flash operation status
[0]     RnB    0:NAND Flash memory busy 1:NAND Flash memory ready to operate

NFECC 0x4E000014 R NAND Flash ECC (Error Correction Code) register
[23:16]   Error Correction Code #2
[15:8]     #1
[7:0]       #0

 

 

PWM Timer 寄存器

2009-05-24 16:59

PWM TIMER

TCFG0 0x51000000 R/W Configures the two 8-bit prescalers
TCFG1 0x51000004 R/W 5-MUX & DMA mode selecton register
TCON 0x51000008 R/W Timer control register
TCNTB0 0x5100000C R/W Timer 0 count buffer register
TCMPB0 0x51000010 R/W Timer 0 compare buffer register
TCNTO0 0x51000014 R Timer 0 count observation register
TCNTB1 0x51000018 R/W Timer 1 count buffer register
TCMPB1 0x5100001C R/W Timer 1 compare buffer register
TCNTO1 0x51000020 R Timer 1 count observation register
TCNTB2 0x51000024 R/W Timer 2 count buffer register
TCMPB2 0x51000028 R/W Timer 2 compare buffer register
TCNTO2 0x5100002C R Timer 2 count observation register
TCNTB3 0x51000030 R/W Timer 3 count buffer register
TCMPB3 0x51000034 R/W Timer 3 compare buffer register
TCNTO3 0x51000038 R Timer 3 count observation register
TCNTB4 0x5100003C R/W Timer 4 count buffer register
TCNTO4 0x51000040 R Timer 4 count observation register

TCFG0 0x51000000 R/W Configures the two 8-bit prescalers
[23:16] Dead zone length
[15: 8] Prescaler 1 These 8 bits determine prescaler value for Timer 2, 3 and 4.
[ 7: 0] Prescaler 1   for Timer 1 and 0.

TCFG1 0x51000004 R/W 5-MUX & DMA mode selecton register
[23:20] DMA mode Select DMA: 0000=NoSelect; 0001=Timer0; 0010=Timer1; 0011=Timer2; 0100=Timer3; 0101=Timer4; 0110=Reserved
[19:16] MUX4 Select MUX input for PWM Timer4:0000=1/2;0001=1/4;0010=1/8; 0011=1/16; 01xx=External TCLK1
[15:12] MUX3 for Timer3
[11: 8] MUX2 for Timer2
[ 7: 4] MUX1 for Timer1
[ 3: 0] MUX0 for Timer0

TCON 0x51000008 R/W Timer control register
[22] Timer 4 auto reload on/off 0=One-shot   1=Interval mode(auto reload)
[21] Timer 4 manual update       0=No operation 1=Update TCNTB4
[20] Timer 4 start/stop                0=Stop 1=Strat for Timer 4
[19] Timer 3 auto reload on/off
[18] Timer 3 output inverter on off 0=Inverter off    1=Inverter on for TOUT3
[17] Timer 3 manual update
[16] Timer 3 start/stop
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]   Timer 1 start/stop
[7:5]   Reserved
[4]    Dead zone enable
[3]    Timer 0 auto reload on/off
[2]     Timer 0 output inverter on/off
[1]    Timer 0 manual update
[0]     Timer 0 start/stop

TCNTB0 0x5100000C R/W Timer 0 count buffer register
[15:0] Timer 0 count buffer register
TCMPB0 0x51000010 R/W Timer 0 compare buffer register
[15:0] Timer 0 compare buffer register
TCNTO0 0x51000014 R Timer 0 count observation register
[15:0] Timer 0 observation register (计数观察寄存器)

TCNTB1 0x51000018 R/W Timer 1 count buffer register
TCMPB1 0x5100001C R/W Timer 1 compare buffer register
TCNTO1 0x51000020 R Timer 1 count observation register

TCNTB2 0x51000024 R/W Timer 2 count buffer register
TCMPB2 0x51000028 R/W Timer 2 compare buffer register
TCNTO2 0x5100002C R Timer 2 count observation register

TCNTB3 0x51000030 R/W Timer 3 count buffer register
TCMPB3 0x51000034 R/W Timer 3 compare buffer register
TCNTO3 0x51000038 R Timer 3 count observation register

TCNTB4 0x5100003C R/W Timer 4 count buffer register
TCNTO4 0x51000040 R Timer 4 count observation register

 

 

 

WATCHDOG TIMER

2009-05-24 18:35

WATCHDOG TIMER

OVERVIEW
The S3C2440A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions
such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The
watchdog timer generates the reset signal for 128 PCLK cycles.

t_watchdog = 1/[ PCLK / (Prescaler value + 1) / Division_factor ]

Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). In this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts.

When the S3C2440A is in debug mode using Embedded ICE, the watchdog timer must not operate.

The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C2440A restart on mal-function after its power on; if controller restart is not desired, the Watchdog timer should be disabled.
If the user wants to use the normal timer provided by the Watchdog timer, enable the interrupt and disable the Watchdog timer.

WTCON 0x53000000 R/W Watchdog timer control register 0x8021
[15:8] Prescaler value 0--255
[5]       Watchdog timer. Enable or disable bit of Watchdog timer.
[4:3]    Clock select. Determine the clock division factor. 00=16;01=32;10=64;11=128
[2]       Interrupt generation. Enable or disable bit of the interrupt. 0=Disable;1=Enable
[0]       Reset enable/disable. Enable or disable bit of watchdog timer output for reset signal.
            1=Assert reset signal of the S3C2440A at watchdog time-out
           0=Disable the reset function of the watchdog timer.

WTDAT 0x53000004 R/W Watchdog timer data register 0x8000
[15:0] Count reload value

WTCNT 0x53000008 R/W Watchdog timer count register 0x8000
[15:0] Count value

 

S3C2440 IO口寄存器地址

2009-05-10 00:26

S3C2440 IO口寄存器地址

GPACON：0x56000000，默认7FFFFF
GPADAT：0x56000004
GPA0：ADDR0
GPA1~GPA11：ADDR16~ADDR26
GPA12~GPA16： nGCS1~nGCS5
GPA17 CLE
GPA18 ALE
GPA19 nFWE
GPA20 nFRE
GPA21 nRSTOUT
GPA22 nFCE

GPBCON：0x56000010，默认0x0
GPBDAT：0x56000014，
GPBUP：0x56000018，默认0x0
GPB0~GPB3：TOUT0~TOUT3
GPB4 TCLK0
GPB5 nXBACK
GPB6 nXBREQ
GPB7 nXDACK1
GPB8 nXDREQ1
GPB9 nXDACK0
GPB10 nXDREQ0

GPCCON 0x56000020
GPCDAT 0x56000024
GPCUP 0x56000028
GPC0 LEND
GPC1 VCLK
GPC2 VLINE
GPC3 VFRAME
GPC4 VM
GPC5 LCDVF0
GPC6 LCDVF1
GPC7 LCDVF2
GPC8~GPC15 VD0~VD7

GPFCON 0x56000050
GPFDAT 0x56000054
GPFUP 0x56000058
GPB0~GPB7 EINT0~EINT7