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分类: LINUX

2012-04-23 11:37:06

A restrictive environment: Just C++ and Python with an event queue and a bunch of APIs you can choose to ignore。
 
A framework for event-driven simulation: Events, objects, statistics, configuration
A collection of predefined object models: CPUs, caches, busses, devices, etc
 
Execution modes: System-call Emulation (SE) &
Full-System (FS)
 ISAs: Alpha, ARM, MIPS, Power, SPARC, x86
 CPU models: AtomicSimple, TimingSimple, InOrder, and O3
 Cache coherence protocols: broadcast-based, directories,
etc.
 Interconnection networks: Simple & Garnet (Princeton,MIT)
 Devices: NICs, IDE controller, etc.
 Multiple systems: communicate over TCP/IP
 
Platforms
 Linux, BSD, MacOS, Solaris, etc.
 Little endian machines
 Some architectures support big endian
 64-bit machines help a lot
 Tools
 GCC/G++ 3.4.6+
 Most frequently tested with 4.2-4.5
 Python 2.4+
 SCons 0.98.1+
 We generally test versions 0.98.5 and 1.2.0

 SWIG 1.3.31+

 
build//
 configs
 By convention, usually _
 ALPHA_SE (Alpha syscall emulation)
 ALPHA_FS (Alpha full system)
 Other ISAs: ARM, MIPS, POWER, SPARC, X86
 Sometimes followed by Ruby protocol:
 ALPHA_SE_MOESI_hammer
 You can define your own configs
 binary
 gem5.debug – debug build, symbols, tracing, assert
 gem5.opt – optimized build, symbols, tracing, assert
 gem5.fast – optimized build, no debugging, no symbols, no tracing, no assertions
 gem5.prof – gem5.fast + profiling support
 
Full system (FS)
 For booting operating systems
 Models bare hardware, including devices
 Interrupts, exceptions, privileged instructions, fault handlers
 Syscall emulation (SE)
 For running individual applications, or set of applications on MP/SMT
 Models user-visible ISA plus common system calls
 System calls emulated, typ. by calling host OS
 Simplified address translation model, no scheduling
 
Three access modes: Functional, Atomic, Timing
 Selected by choosing function on initial Port:
 sendFunctional(), sendAtomic(), sendTiming()
 Functional mode:
 Just “make it happen”
 Used for loading binaries, debugging, etc.
 Accesses happen instantaneously updating data everywhere in the hierarchy
 If devices contain queues of packets they must be scanned and updated as well
 
 
Atomic mode:
 Requests complete before sendAtomic() returns
 Models state changes (cache fills, coherence, etc.)
 Returns approx. latency w/o contention or queuing delay
 Used for fast simulation, fast forwarding, or warming caches
 Timing mode:
 Models all timing/queuing in the memory system
 Split transaction
 sendTiming() just initiates send of request to target
Atomic and Timing accesses can not coexist in system
 Target later calls sendTiming() to send response packet
 
 
Full-System & Syscall Emulation
 Alpha
 ARM
 SPARC
 x86
Syscall Emulation
 MIPS
 

Alpha
 Alpha 21264 including the BWX, MVI, FIX, and CIXA
 21164 PAL code.
 Syscall Emulation
 Linux or Tru64 binaries
 Simple Atomic, Simple Timing, In-Order, Out-of-Order CPU models
 Full system
 Linux or FreeBSD
 Simple Atomic, Simple Timing, In-Order, Out-of-Order CPU models
 Four-cores in a normal Tsunami system
 Also gem5 big Tsunami support 64 cores
 Custom PAL code and kernel patches required POWER
 
ARM
 ARMv7-A, Thumb, Thumb2, MP, VFPv3, NEON
 Doesn’t (yet) include TrustZone, ThumbEE, Virtualization,LPAE
 Syscall Emulation
 EABI Linux binaries - no OABI
 Simple Atomic, Simple Timing, Out-of-Order CPU models
 Full system
 Linux or Android
 Simple Atomic, Simple Timing, Out-of-Order CPU models
 Four-cores in a normal ARM RealView system
 No kernel patches required
 Also supports frame buffer, and control via VNC
 Can run X11, Android, Web browsers, etc
 
SPARC
 UltraSPARC Architecture 2005
 Syscall Emulation
 Linux or Solaris binaries
 Simple Atomic, Simple Timing, Out-of-Order CPU models
 Full system
 Solaris
 Single core of a UltraSPARC T1 (Niagara) processor
 Simple Atomic CPU model only
 Significant progress on MP, but not actively developed
 
Parts of an ISA
 Parameterization
 Number of registers
 Endianness
 Page size
 Specialized objects
 TLBs
 Faults
 Control state
 Interrupt controller
 Instructions
 Instructions themselves
 Decoding mechanism
 
Supported CPU Models
 AtomicSimpleCPU
 TimingSimpleCPU
 InOrderCPU
 O3CPU
 CPU Model Internals
 Parameters
 Time Buffers
 Key Interfaces
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给主人留下些什么吧!~~

bruce4211162013-05-02 18:46:47

大哥你好,请问这个从事啥工作需要GEM5?还是单纯理论研究啊?

Jiker48362012-04-25 10:43:05

我也是刚刚在学。这个做仿真有点难度,你如果仿真arm之类的,我觉得你可以用skyeye。比较方便做出一个仿真结果。